<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns:m="http://schemas.microsoft.com/office/2004/12/omml" xmlns="http://www.w3.org/TR/REC-html40"> <head> <meta http-equiv="Content-Type" content="text/html; charset=iso-2022-jp"> <meta name="Generator" content="Microsoft Word 15 (filtered medium)"> <style></style> </head> <body lang="EN-US" link="#0563C1" vlink="#954F72"> <div class="WordSection1"> [AMD Public Use]<o:p></o:p> <o:p> </o:p> Hello Tao,<o:p></o:p> <o:p> </o:p> That is an interesting suggestion, I agree that there is a little bit of duplicate code with the same for loops being used in multiple functions.<o:p></o:p> <o:p> </o:p> My only concern with implementing the loops in a macro is code readability.<o:p></o:p> <o:p> </o:p> I’ll have to think about the trade off between the duplicate code and code readability more.<o:p></o:p> <o:p> </o:p> Thank you,<o:p></o:p> John Clements<o:p></o:p> <o:p> </o:p> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in"> From: Zhou1, Tao <Tao.Zhou1@amd.com> Sent: Friday, January 3, 2020 10:53 AM To: Clements, John <John.Clements@amd.com>; amd-gfx@lists.freedesktop.org; Zhang, Hawking <Hawking.Zhang@amd.com> Subject: RE: [PATCH] drm/amdgpu: resolved bug in UMC 6 error counter query<o:p></o:p> </div> </div> <o:p> </o:p> [AMD Public Use]<o:p></o:p> <o:p> </o:p> I think we can implement it by only updating amdgpu_umc_for_each_channel macro, here is an example:<o:p></o:p> <o:p> </o:p> #define amdgpu_umc_for_each_channel(func) \<o:p></o:p> struct ras_err_data *err_data = \<o:p></o:p> (struct ras_err_data *)ras_error_status; \<o:p></o:p> uint32_t umc_inst, channel_inst, umc_reg_offset, channel_index; \<o:p></o:p> for (umc_inst = 0; umc_inst < adev->umc.umc_inst_num; \<o:p></o:p> umc_inst++) { \<o:p></o:p> umc_reg_offset = adev->umc.inst_offs * umc_inst; \<o:p></o:p> for (channel_inst = 0; \<o:p></o:p> channel_inst < adev->umc.channel_inst_num; \<o:p></o:p> channel_inst++) { \<o:p></o:p> /* get channel index of interleaved memory */ \<o:p></o:p> channel_index = adev->umc.channel_idx_tbl[\<o:p></o:p> umc_inst * adev->umc.channel_inst_num + channel_inst]; \<o:p></o:p> (func)(adev, err_data, umc_reg_offset, channel_index); \<o:p></o:p> /* increase register offset for next channel */ \<o:p></o:p> umc_reg_offset += adev->umc.channel_offs; \<o:p></o:p> } \<o:p></o:p> }<o:p></o:p> <o:p> </o:p> Regards,<o:p></o:p> Tao<o:p></o:p> <div style="border:none;border-left:solid blue 1.5pt;padding:0in 0in 0in 4.0pt"> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in"> From: Clements, John <<a href="mailto:John.Clements@amd.com">John.Clements@amd.com</a>> Sent: 2020年1月2日 18:31 To: <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a>; Zhang, Hawking <<a href="mailto:Hawking.Zhang@amd.com">Hawking.Zhang@amd.com</a>>; Zhou1, Tao <<a href="mailto:Tao.Zhou1@amd.com">Tao.Zhou1@amd.com</a>> Subject: [PATCH] drm/amdgpu: resolved bug in UMC 6 error counter query<o:p></o:p> </div> </div> <o:p> </o:p> [AMD Official Use Only - Internal Distribution Only]<o:p></o:p> <o:p> </o:p> Added patch to resolve following issue where error counter detection was not iterating over all UMC instances/channels.<o:p></o:p> Removed support for accessing UMC error counters via MMIO.<o:p></o:p> <o:p> </o:p> Thank you,<o:p></o:p> John Clements<o:p></o:p> </div> </div> </body> </html>