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<p class="msipheader4d0fcdd7" style="margin:0cm;margin-bottom:.0001pt"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:#0078D7">[AMD Official Use Only - Internal Distribution Only]</span><o:p></o:p></p>
<p class="MsoNormal"><span style="font-size:12.0pt;font-family:宋体"><o:p> </o:p></span></p>
<p class="MsoNormal">Reviewed-by: Tao Zhou <<a href="mailto:tao.zhou1@amd.com">tao.zhou1@amd.com</a>><o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">BTW, are you sure replacing RREG32/WREG32 with RREG32/WREG32_PCIE is also necessary to fix the bug?<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Regards,<o:p></o:p></p>
<p class="MsoNormal">Tao<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><b>From:</b> Clements, John <John.Clements@amd.com> <br>
<b>Sent:</b> 2020<span lang="ZH-CN" style="font-family:宋体">年</span>1<span lang="ZH-CN" style="font-family:宋体">月</span>7<span lang="ZH-CN" style="font-family:宋体">日</span> 11:54<br>
<b>To:</b> amd-gfx@lists.freedesktop.org; dl.srdc_lnx_ras <dl.srdc_lnx_ras@amd.com><br>
<b>Subject:</b> [PATCH] drm/amdgpu: resolved bug in UMC RAS CE query<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
<p class="msipheader4d0fcdd7" style="margin:0cm;margin-bottom:.0001pt"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:#0078D7">[AMD Official Use Only - Internal Distribution Only]</span><o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Submitting patch to access CE registers via SMN and disable UMC indexing mode.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Thank you,<o:p></o:p></p>
<p class="MsoNormal">John Clements<o:p></o:p></p>
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