<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns:m="http://schemas.microsoft.com/office/2004/12/omml" xmlns="http://www.w3.org/TR/REC-html40">
<head>
<meta http-equiv="Content-Type" content="text/html; charset=iso-2022-jp">
<meta name="Generator" content="Microsoft Word 15 (filtered medium)">
<style><!--
/* Font Definitions */
@font-face
{font-family:SimSun;
panose-1:2 1 6 0 3 1 1 1 1 1;}
@font-face
{font-family:"Cambria Math";
panose-1:2 4 5 3 5 4 6 3 2 4;}
@font-face
{font-family:Calibri;
panose-1:2 15 5 2 2 2 4 3 2 4;}
@font-face
{font-family:"MS PGothic";
panose-1:2 11 6 0 7 2 5 8 2 4;}
@font-face
{font-family:"\@SimSun";
panose-1:2 1 6 0 3 1 1 1 1 1;}
@font-face
{font-family:"\@MS PGothic";}
/* Style Definitions */
p.MsoNormal, li.MsoNormal, div.MsoNormal
{margin:0in;
margin-bottom:.0001pt;
font-size:11.0pt;
font-family:"Calibri",sans-serif;
mso-fareast-language:JA;}
a:link, span.MsoHyperlink
{mso-style-priority:99;
color:#0563C1;
text-decoration:underline;}
a:visited, span.MsoHyperlinkFollowed
{mso-style-priority:99;
color:#954F72;
text-decoration:underline;}
p.msonormal0, li.msonormal0, div.msonormal0
{mso-style-name:msonormal;
mso-margin-top-alt:auto;
margin-right:0in;
mso-margin-bottom-alt:auto;
margin-left:0in;
font-size:11.0pt;
font-family:"Calibri",sans-serif;
mso-fareast-language:JA;}
p.msipheader4d0fcdd7, li.msipheader4d0fcdd7, div.msipheader4d0fcdd7
{mso-style-name:msipheader4d0fcdd7;
mso-margin-top-alt:auto;
margin-right:0in;
mso-margin-bottom-alt:auto;
margin-left:0in;
font-size:11.0pt;
font-family:"Calibri",sans-serif;
mso-fareast-language:JA;}
span.EmailStyle19
{mso-style-type:personal;
font-family:"Calibri",sans-serif;
color:windowtext;}
span.EmailStyle20
{mso-style-type:personal;
font-family:"Calibri",sans-serif;
color:windowtext;}
span.EmailStyle21
{mso-style-type:personal-reply;
font-family:"Calibri",sans-serif;
color:windowtext;}
.MsoChpDefault
{mso-style-type:export-only;
font-size:10.0pt;}
@page WordSection1
{size:8.5in 11.0in;
margin:1.0in 1.0in 1.0in 1.0in;}
div.WordSection1
{page:WordSection1;}
--></style><!--[if gte mso 9]><xml>
<o:shapedefaults v:ext="edit" spidmax="1026" />
</xml><![endif]--><!--[if gte mso 9]><xml>
<o:shapelayout v:ext="edit">
<o:idmap v:ext="edit" data="1" />
</o:shapelayout></xml><![endif]-->
</head>
<body lang="EN-US" link="#0563C1" vlink="#954F72">
<div class="WordSection1">
<p class="msipheader4d0fcdd7" style="margin:0in;margin-bottom:.0001pt"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:#0078D7">[AMD Official Use Only - Internal Distribution Only]</span><o:p></o:p></p>
<p class="MsoNormal"><span style="font-size:12.0pt;font-family:"MS PGothic",sans-serif"><o:p> </o:p></span></p>
<p class="MsoNormal">Not necessary, but I wanted to make the register all access’ consistent.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">In a future patch I shall replace the MMIO register offsets with the SMN offsets directly instead of having *4 all over the place.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Thank you,<o:p></o:p></p>
<p class="MsoNormal">John Clements<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><b>From:</b> Zhou1, Tao <Tao.Zhou1@amd.com> <br>
<b>Sent:</b> Tuesday, January 7, 2020 1:59 PM<br>
<b>To:</b> Clements, John <John.Clements@amd.com>; amd-gfx@lists.freedesktop.org; dl.srdc_lnx_ras <dl.srdc_lnx_ras@amd.com><br>
<b>Subject:</b> RE: [PATCH] drm/amdgpu: resolved bug in UMC RAS CE query<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
<p class="msipheader4d0fcdd7" style="margin:0in;margin-bottom:.0001pt"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:#0078D7">[AMD Official Use Only - Internal Distribution Only]</span><o:p></o:p></p>
<p class="MsoNormal"><span style="font-size:12.0pt;font-family:SimSun"><o:p> </o:p></span></p>
<p class="MsoNormal">Reviewed-by: Tao Zhou <<a href="mailto:tao.zhou1@amd.com">tao.zhou1@amd.com</a>><o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">BTW, are you sure replacing RREG32/WREG32 with RREG32/WREG32_PCIE is also necessary to fix the bug?<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Regards,<o:p></o:p></p>
<p class="MsoNormal">Tao<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><b>From:</b> Clements, John <<a href="mailto:John.Clements@amd.com">John.Clements@amd.com</a>>
<br>
<b>Sent:</b> 2020<span lang="ZH-CN" style="font-family:SimSun;mso-fareast-language:ZH-CN">年</span>1<span lang="ZH-CN" style="font-family:SimSun;mso-fareast-language:ZH-CN">月</span>7<span lang="ZH-CN" style="font-family:SimSun;mso-fareast-language:ZH-CN">日</span>
11:54<br>
<b>To:</b> <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a>; dl.srdc_lnx_ras <<a href="mailto:dl.srdc_lnx_ras@amd.com">dl.srdc_lnx_ras@amd.com</a>><br>
<b>Subject:</b> [PATCH] drm/amdgpu: resolved bug in UMC RAS CE query<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
<p class="msipheader4d0fcdd7" style="margin:0in;margin-bottom:.0001pt"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:#0078D7">[AMD Official Use Only - Internal Distribution Only]</span><o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Submitting patch to access CE registers via SMN and disable UMC indexing mode.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Thank you,<o:p></o:p></p>
<p class="MsoNormal">John Clements<o:p></o:p></p>
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