<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns:m="http://schemas.microsoft.com/office/2004/12/omml" xmlns="http://www.w3.org/TR/REC-html40"> <head> <meta http-equiv="Content-Type" content="text/html; charset=us-ascii"> <meta name="Generator" content="Microsoft Word 15 (filtered medium)"> <style></style> </head> <body lang="EN-CA" link="blue" vlink="purple"> <div class="WordSection1"> <p class="MsoNormal"><span style="mso-fareast-language:EN-US">Thanks Alex!<o:p></o:p></span></p> <p class="MsoNormal"><span style="mso-fareast-language:EN-US"><o:p> </o:p></span></p> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0cm 0cm 0cm"> <p class="MsoNormal"><b><span lang="EN-US">From:</span></b><span lang="EN-US"> Deucher, Alexander <Alexander.Deucher@amd.com> <br> <b>Sent:</b> February 25, 2020 1:16 PM<br> <b>To:</b> Khaire, Rohit <Rohit.Khaire@amd.com>; amd-gfx@lists.freedesktop.org<br> <b>Subject:</b> Re: [PATCH] SWDEV-220585 - Navi12 L1 policy GC regs WAR #1<o:p></o:p></span></p> </div> </div> <p class="MsoNormal"><o:p> </o:p></p> <p style="margin:15.0pt"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:#317100">[AMD Public Use]<o:p></o:p></span></p> <p class="MsoNormal"><o:p> </o:p></p> <div> <div> <p class="MsoNormal"><span style="font-size:12.0pt;color:black">Please fix up the patch title. E.g.,<o:p></o:p></span></p> </div> <div> <p class="MsoNormal"><span style="font-size:12.0pt;color:black">drm/amdgpu: Don't write </span><span style="color:black">GCVM_L2_CNTL* regs on navi12 VF</span><span style="font-size:12.0pt;color:black"><o:p></o:p></span></p> </div> <div> <p class="MsoNormal"><span style="font-size:12.0pt;color:black"><o:p> </o:p></span></p> </div> <div> <p class="MsoNormal"><span style="font-size:12.0pt;color:black">With that fixed, patch is:<o:p></o:p></span></p> </div> <div> <p class="MsoNormal"><span style="font-size:12.0pt;color:black">Reviewed-by: Alex <a href="mailto:Deucher@amd.com">Deucher@amd.com</a>><o:p></o:p></span></p> </div> <div> <p class="MsoNormal"><span style="font-size:12.0pt;color:black"><o:p> </o:p></span></p> </div> <div class="MsoNormal" align="center" style="text-align:center"> <hr size="2" width="98%" align="center"> </div> <div id="divRplyFwdMsg"> <p class="MsoNormal"><b><span style="color:black">From:</span></b><span style="color:black"> amd-gfx <<a href="mailto:amd-gfx-bounces@lists.freedesktop.org">amd-gfx-bounces@lists.freedesktop.org</a>> on behalf of Rohit Khaire <<a href="mailto:Rohit.Khaire@amd.com">Rohit.Khaire@amd.com</a>><br> <b>Sent:</b> Friday, February 21, 2020 3:24 PM<br> <b>To:</b> <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a> <<a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a>><br> <b>Cc:</b> Khaire, Rohit <<a href="mailto:Rohit.Khaire@amd.com">Rohit.Khaire@amd.com</a>><br> <b>Subject:</b> [PATCH] SWDEV-220585 - Navi12 L1 policy GC regs WAR #1</span> <o:p> </o:p></p> <div> <p class="MsoNormal"> <o:p></o:p></p> </div> </div> <div> <div> <p class="MsoNormal">This change disables programming of GCVM_L2_CNTL* regs on VF.<br> <br> Signed-off-by: Rohit Khaire <<a href="mailto:Rohit.Khaire@amd.com">Rohit.Khaire@amd.com</a>><br> ---<br> drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 12 +++++++++---<br> 1 file changed, 9 insertions(+), 3 deletions(-)<br> <br> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c<br> index b70c7b483c24..e0654a216ab5 100644<br> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c<br> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c<br> @@ -135,6 +135,10 @@ static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev)<br> {<br> uint32_t tmp;<br> <br> + /* These regs are not accessible for VF, PF will program these in SRIOV */<br> + if (amdgpu_sriov_vf(adev))<br> + return;<br> +<br> /* Setup L2 cache */<br> tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);<br> tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);<br> @@ -298,9 +302,11 @@ void gfxhub_v2_0_gart_disable(struct amdgpu_device *adev)<br> ENABLE_ADVANCED_DRIVER_MODEL, 0);<br> WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);<br> <br> - /* Setup L2 cache */<br> - WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);<br> - WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0);<br> + if (!amdgpu_sriov_vf(adev)) {<br> + /* Setup L2 cache */<br> + WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);<br> + WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0);<br> + }<br> }<br> <br> /**<br> -- <br> 2.17.1<br> <br> _______________________________________________<br> amd-gfx mailing list<br> <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a><br> <a href="https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Calexander.deucher%40amd.com%7C52705cf7b1bc4750932a08d7b70c0e38%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637179135079462923&sdata=6YT8MUoBGMujktD%2BoYjEcxCAq2TE4gt7CO7GO4mGpoc%3D&reserved=0">https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Calexander.deucher%40amd.com%7C52705cf7b1bc4750932a08d7b70c0e38%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637179135079462923&sdata=6YT8MUoBGMujktD%2BoYjEcxCAq2TE4gt7CO7GO4mGpoc%3D&reserved=0</a><o:p></o:p></p> </div> </div> </div> </div> </body> </html>