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[AMD Public Use]<br>
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Please fix up the patch title. E.g.,</div>
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drm/amdgpu: <font face="Calibri, sans-serif">Don't write <font size="2"><span style="font-size:11pt">GCVM_L2_CNTL* regs on navi12 VF</span></font></font><br>
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With that fixed, patch is:</div>
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Reviewed-by: Alex Deucher@amd.com><br>
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<div id="divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" face="Calibri, sans-serif" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Rohit Khaire <Rohit.Khaire@amd.com><br>
<b>Sent:</b> Friday, February 21, 2020 3:24 PM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Khaire, Rohit <Rohit.Khaire@amd.com><br>
<b>Subject:</b> [PATCH] SWDEV-220585 - Navi12 L1 policy GC regs WAR #1</font>
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<div class="PlainText">This change disables programming of GCVM_L2_CNTL* regs on VF.<br>
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Signed-off-by: Rohit Khaire <Rohit.Khaire@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 12 +++++++++---<br>
1 file changed, 9 insertions(+), 3 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c<br>
index b70c7b483c24..e0654a216ab5 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c<br>
@@ -135,6 +135,10 @@ static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev)<br>
{<br>
uint32_t tmp;<br>
<br>
+ /* These regs are not accessible for VF, PF will program these in SRIOV */<br>
+ if (amdgpu_sriov_vf(adev))<br>
+ return;<br>
+<br>
/* Setup L2 cache */<br>
tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);<br>
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);<br>
@@ -298,9 +302,11 @@ void gfxhub_v2_0_gart_disable(struct amdgpu_device *adev)<br>
ENABLE_ADVANCED_DRIVER_MODEL, 0);<br>
WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);<br>
<br>
- /* Setup L2 cache */<br>
- WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);<br>
- WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0);<br>
+ if (!amdgpu_sriov_vf(adev)) {<br>
+ /* Setup L2 cache */<br>
+ WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);<br>
+ WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0);<br>
+ }<br>
}<br>
<br>
/**<br>
-- <br>
2.17.1<br>
<br>
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