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[AMD Public Use]<br>
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Is there any reason to not just use this for bare metal as well?</div>
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Alex</div>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of jianzh <Jiange.Zhao@amd.com><br>
<b>Sent:</b> Thursday, February 27, 2020 6:21 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Deng, Emily <Emily.Deng@amd.com>; Zhao, Jiange <Jiange.Zhao@amd.com>; Liu, Monk <Monk.Liu@amd.com><br>
<b>Subject:</b> [PATCH] drm/amdgpu/sriov: Use VF-accessible register for gpu_clock_count</font>
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<div class="PlainText">Navi12 VK CTS subtest timestamp.calibrated.dev_domain_test failed<br>
because mmRLC_CAPTURE_GPU_CLOCK_COUNT register cannot be<br>
written in VF due to security policy.<br>
<br>
Solution: use a VF-accessible timestamp register pair<br>
mmGOLDEN_TSC_COUNT_LOWER/UPPER for SRIOV case.<br>
<br>
Signed-off-by: jianzh <Jiange.Zhao@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 13 ++++++++++---<br>
1 file changed, 10 insertions(+), 3 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c<br>
index 44f00ec..8787a46 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c<br>
@@ -35,6 +35,8 @@<br>
<br>
#include "gc/gc_10_1_0_offset.h"<br>
#include "gc/gc_10_1_0_sh_mask.h"<br>
+#include "smuio/smuio_11_0_0_offset.h"<br>
+#include "smuio/smuio_11_0_0_sh_mask.h"<br>
#include "navi10_enum.h"<br>
#include "hdp/hdp_5_0_0_offset.h"<br>
#include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"<br>
@@ -3920,9 +3922,14 @@ static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)<br>
<br>
amdgpu_gfx_off_ctrl(adev, false);<br>
mutex_lock(&adev->gfx.gpu_clock_mutex);<br>
- WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);<br>
- clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |<br>
- ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);<br>
+ if (!amdgpu_sriov_vf(adev)) {<br>
+ WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);<br>
+ clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |<br>
+ ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);<br>
+ } else {<br>
+ clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) |<br>
+ ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);<br>
+ }<br>
mutex_unlock(&adev->gfx.gpu_clock_mutex);<br>
amdgpu_gfx_off_ctrl(adev, true);<br>
return clock;<br>
-- <br>
2.7.4<br>
<br>
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