<html> <head> <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1"> <style type="text/css" style="display:none;"> P {margin-top:0;margin-bottom:0;} </style> </head> <body dir="ltr"> <div style="font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);"> Let's just switch everyone over. I think this should work for both bare metal and SR-IOV. Fewer code pathes to maintain. Feel free to do it as a follow up patch.</div> <div style="font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);"> <br> </div> <div style="font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);"> Thanks,<br> </div> <div style="font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);"> <br> </div> <div style="font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);"> Alex</div> <div style="font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);"> <br> </div> <div id="appendonsend"></div> <div style="font-family:Calibri,Arial,Helvetica,sans-serif; font-size:12pt; color:rgb(0,0,0)"> <br> </div> <hr tabindex="-1" style="display:inline-block; width:98%"> <div id="divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" face="Calibri, sans-serif" color="#000000"><b>From:</b> Zhao, Jiange <Jiange.Zhao@amd.com><br> <b>Sent:</b> Thursday, February 27, 2020 10:02 PM<br> <b>To:</b> Deucher, Alexander <Alexander.Deucher@amd.com>; amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br> <b>Cc:</b> Deng, Emily <Emily.Deng@amd.com>; Liu, Monk <Monk.Liu@amd.com><br> <b>Subject:</b> Re: [PATCH] drm/amdgpu/sriov: Use VF-accessible register for gpu_clock_count</font> <div> </div> </div> <div dir="ltr"> <div style="font-family:Calibri,Arial,Helvetica,sans-serif; font-size:12pt; color:rgb(0,0,0)"> Hi,</div> <div style="font-family:Calibri,Arial,Helvetica,sans-serif; font-size:12pt; color:rgb(0,0,0)"> <br> </div> <div style="font-family:Calibri,Arial,Helvetica,sans-serif; font-size:12pt; color:rgb(0,0,0)"> I got feedback from Linux team and they simply don't want to change.</div> <div style="font-family:Calibri,Arial,Helvetica,sans-serif; font-size:12pt; color:rgb(0,0,0)"> <br> </div> <div style="font-family:Calibri,Arial,Helvetica,sans-serif; font-size:12pt; color:rgb(0,0,0)"> I believe that it would work for bare metal as well.</div> <div style="font-family:Calibri,Arial,Helvetica,sans-serif; font-size:12pt; color:rgb(0,0,0)"> <br> </div> <div style="font-family:Calibri,Arial,Helvetica,sans-serif; font-size:12pt; color:rgb(0,0,0)"> Jiange<br> </div> <div id="x_appendonsend"></div> <hr tabindex="-1" style="display:inline-block; width:98%"> <div id="x_divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" face="Calibri, sans-serif" color="#000000"><b>From:</b> Deucher, Alexander <Alexander.Deucher@amd.com><br> <b>Sent:</b> Thursday, February 27, 2020 10:23 PM<br> <b>To:</b> Zhao, Jiange <Jiange.Zhao@amd.com>; amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br> <b>Cc:</b> Deng, Emily <Emily.Deng@amd.com>; Liu, Monk <Monk.Liu@amd.com><br> <b>Subject:</b> Re: [PATCH] drm/amdgpu/sriov: Use VF-accessible register for gpu_clock_count</font> <div> </div> </div> <div dir="ltr"> <p style="margin-top: 0px; margin-bottom: 0px;margin-top: 0px; margin-bottom: 0px;font-family:Arial; font-size:10pt; color:#317100; margin:15pt" align="Left"> [AMD Public Use]<br> </p> <br> <div> <div style="font-family:Calibri,Arial,Helvetica,sans-serif; font-size:12pt; color:rgb(0,0,0)"> Is there any reason to not just use this for bare metal as well?</div> <div style="font-family:Calibri,Arial,Helvetica,sans-serif; font-size:12pt; color:rgb(0,0,0)"> <br> </div> <div style="font-family:Calibri,Arial,Helvetica,sans-serif; font-size:12pt; color:rgb(0,0,0)"> Alex</div> <div style="font-family:Calibri,Arial,Helvetica,sans-serif; font-size:12pt; color:rgb(0,0,0)"> <br> </div> <div id="x_x_appendonsend"></div> <hr tabindex="-1" style="display:inline-block; width:98%"> <div id="x_x_divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" face="Calibri, sans-serif" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of jianzh <Jiange.Zhao@amd.com><br> <b>Sent:</b> Thursday, February 27, 2020 6:21 AM<br> <b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br> <b>Cc:</b> Deng, Emily <Emily.Deng@amd.com>; Zhao, Jiange <Jiange.Zhao@amd.com>; Liu, Monk <Monk.Liu@amd.com><br> <b>Subject:</b> [PATCH] drm/amdgpu/sriov: Use VF-accessible register for gpu_clock_count</font> <div> </div> </div> <div class="x_x_BodyFragment"><font size="2"><span style="font-size:11pt"> <div class="x_x_PlainText">Navi12 VK CTS subtest timestamp.calibrated.dev_domain_test failed<br> because mmRLC_CAPTURE_GPU_CLOCK_COUNT register cannot be<br> written in VF due to security policy.<br> <br> Solution: use a VF-accessible timestamp register pair<br> mmGOLDEN_TSC_COUNT_LOWER/UPPER for SRIOV case.<br> <br> Signed-off-by: jianzh <Jiange.Zhao@amd.com><br> ---<br> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 13 ++++++++++---<br> 1 file changed, 10 insertions(+), 3 deletions(-)<br> <br> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c<br> index 44f00ec..8787a46 100644<br> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c<br> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c<br> @@ -35,6 +35,8 @@<br> <br> #include "gc/gc_10_1_0_offset.h"<br> #include "gc/gc_10_1_0_sh_mask.h"<br> +#include "smuio/smuio_11_0_0_offset.h"<br> +#include "smuio/smuio_11_0_0_sh_mask.h"<br> #include "navi10_enum.h"<br> #include "hdp/hdp_5_0_0_offset.h"<br> #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"<br> @@ -3920,9 +3922,14 @@ static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)<br> <br> amdgpu_gfx_off_ctrl(adev, false);<br> mutex_lock(&adev->gfx.gpu_clock_mutex);<br> - WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);<br> - clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |<br> - ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);<br> + if (!amdgpu_sriov_vf(adev)) {<br> + WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);<br> + clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |<br> + ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);<br> + } else {<br> + clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) |<br> + ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);<br> + }<br> mutex_unlock(&adev->gfx.gpu_clock_mutex);<br> amdgpu_gfx_off_ctrl(adev, true);<br> return clock;<br> -- <br> 2.7.4<br> <br> _______________________________________________<br> amd-gfx mailing list<br> amd-gfx@lists.freedesktop.org<br> <a href="https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Calexander.deucher%40amd.com%7C9b14a49e41fd48f7138f08d7bb773ed9%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637183993593225894&sdata=jFUVpgeEcTTJbTJ3a7ibAPOyAU3RVF%2FEIN41zaqS0eM%3D&reserved=0">https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Calexander.deucher%40amd.com%7C9b14a49e41fd48f7138f08d7bb773ed9%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637183993593225894&sdata=jFUVpgeEcTTJbTJ3a7ibAPOyAU3RVF%2FEIN41zaqS0eM%3D&reserved=0</a><br> </div> </span></font></div> </div> </div> </div> </body> </html>