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<p class="msipheadera92e061b" style="margin:0in;margin-bottom:.0001pt"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:#0078D7">[AMD Official Use Only - Internal Distribution Only]</span><o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">In the original sequence, if the key bits are not set in the mca_status, the page retirement will not happen and the status register will be cleared.<o:p></o:p></p>
<p class="MsoNormal">If there is a UMC UE, that register will be cleared erroneously 31 times.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">If MCA Status == 0 already from the beginning there is no reason to press forward with the rest of the checks and clear the register.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><b>From:</b> Zhang, Hawking <Hawking.Zhang@amd.com> <br>
<b>Sent:</b> Thursday, March 5, 2020 5:56 PM<br>
<b>To:</b> Clements, John <John.Clements@amd.com>; amd-gfx@lists.freedesktop.org; Li, Dennis <Dennis.Li@amd.com>; Zhou1, Tao <Tao.Zhou1@amd.com>; Chen, Guchun <Guchun.Chen@amd.com><br>
<b>Subject:</b> RE: [PATCH] drm/amdgpu: update page retirement sequence<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
<p class="msipheadera92e061b" style="margin:0in;margin-bottom:.0001pt"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:#0078D7">[AMD Official Use Only - Internal Distribution Only]</span><o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Hi John,<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Can you please explain more on the differences between (a). exit immediately when mca_status is 0 and (b). exit when some of critical field in mca_status is 0?<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Regards,<br>
Hawking<o:p></o:p></p>
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<p class="MsoNormal"><b>From:</b> Clements, John <<a href="mailto:John.Clements@amd.com">John.Clements@amd.com</a>>
<br>
<b>Sent:</b> Thursday, March 5, 2020 17:40<br>
<b>To:</b> <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a>; Zhang, Hawking <<a href="mailto:Hawking.Zhang@amd.com">Hawking.Zhang@amd.com</a>>; Li, Dennis <<a href="mailto:Dennis.Li@amd.com">Dennis.Li@amd.com</a>>; Zhou1, Tao
<<a href="mailto:Tao.Zhou1@amd.com">Tao.Zhou1@amd.com</a>>; Chen, Guchun <<a href="mailto:Guchun.Chen@amd.com">Guchun.Chen@amd.com</a>><br>
<b>Subject:</b> [PATCH] drm/amdgpu: update page retirement sequence<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
<p class="msipheadera92e061b" style="margin:0in;margin-bottom:.0001pt"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:#0078D7">[AMD Official Use Only - Internal Distribution Only]</span><o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">check UMC status and exit prior to making and erroneus register access<o:p></o:p></p>
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