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<p class="msipheader4d0fcdd7" style="margin:0cm;margin-bottom:.0001pt"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:#0078D7">[AMD Official Use Only - Internal Distribution Only]</span><o:p></o:p></p>
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<p class="MsoNormal">Reviewed-by: Tao Zhou <<a href="mailto:tao.zhou1@amd.com">tao.zhou1@amd.com</a>><o:p></o:p></p>
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<p class="MsoNormal"><b>From:</b> Clements, John <John.Clements@amd.com> <br>
<b>Sent:</b> 2020<span lang="ZH-CN" style="font-family:宋体">年</span>3<span lang="ZH-CN" style="font-family:宋体">月</span>5<span lang="ZH-CN" style="font-family:宋体">日</span> 17:40<br>
<b>To:</b> amd-gfx@lists.freedesktop.org; Zhang, Hawking <Hawking.Zhang@amd.com>; Li, Dennis <Dennis.Li@amd.com>; Zhou1, Tao <Tao.Zhou1@amd.com>; Chen, Guchun <Guchun.Chen@amd.com><br>
<b>Subject:</b> [PATCH] drm/amdgpu: update page retirement sequence<o:p></o:p></p>
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<p class="msipheadera92e061b" style="margin:0cm;margin-bottom:.0001pt"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:#0078D7">[AMD Official Use Only - Internal Distribution Only]</span><o:p></o:p></p>
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<p class="MsoNormal">check UMC status and exit prior to making and erroneus register access<o:p></o:p></p>
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