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[AMD Public Use]<br>
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Yes, something like that.</div>
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Alex<br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Kuehling, Felix <Felix.Kuehling@amd.com><br>
<b>Sent:</b> Friday, March 20, 2020 10:47 AM<br>
<b>To:</b> Deucher, Alexander <Alexander.Deucher@amd.com>; Sierra Guiza, Alejandro (Alex) <Alex.Sierra@amd.com>; amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Subject:</b> Re: [PATCH 1/4] drm/amdgpu: add stride to calculate oss ring offsets</font>
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<div class="x_moz-cite-prefix">On 2020-03-20 10:39, Deucher, Alexander wrote:<br>
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[AMD Public Use]<br>
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I'm worried we'll miss a register by accident.  We went with per IP sub drivers to avoid handling complexities around IP differences if possible.  Also the scheme seems like kind of a one off compared to what we do for other IPs.  Can we structure it more like
 how we handle SDMA instancing since it seems to mainly affect IH RB instances?  <br>
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<p>That's more or less what I had in mind, but haven't looked at the SDMA implementation in detail. So do you mean defining macros WREG32_IH_RING(ring, offset, value) and RREG32_IH_RING(ring, offset) analogous to WREG32_SDMA and RREG32_SDMA? It would only apply
 to IH ring-specific registers. Not to other general IH registers.<br>
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<p>Regards,<br>
  Felix<br>
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Alex</div>
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<div id="x_divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" color="#000000" style="font-size:11pt"><b>From:</b> Kuehling, Felix
<a class="x_moz-txt-link-rfc2396E" href="mailto:Felix.Kuehling@amd.com"><Felix.Kuehling@amd.com></a><br>
<b>Sent:</b> Friday, March 20, 2020 10:20 AM<br>
<b>To:</b> Deucher, Alexander <a class="x_moz-txt-link-rfc2396E" href="mailto:Alexander.Deucher@amd.com">
<Alexander.Deucher@amd.com></a>; Sierra Guiza, Alejandro (Alex) <a class="x_moz-txt-link-rfc2396E" href="mailto:Alex.Sierra@amd.com">
<Alex.Sierra@amd.com></a>; <a class="x_moz-txt-link-abbreviated" href="mailto:amd-gfx@lists.freedesktop.org">
amd-gfx@lists.freedesktop.org</a> <a class="x_moz-txt-link-rfc2396E" href="mailto:amd-gfx@lists.freedesktop.org">
<amd-gfx@lists.freedesktop.org></a><br>
<b>Subject:</b> Re: [PATCH 1/4] drm/amdgpu: add stride to calculate oss ring offsets</font>
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<div class="x_x_moz-cite-prefix">On 2020-03-20 10:06, Deucher, Alexander wrote:<br>
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[AMD Public Use]<br>
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This seems kind of complicated and error prone.  I didn't realize the extent to the changes required.  I think it would be better to either add arcturus specific versions of these functions or just go with your original approach and add a new arcturus_ih.c. 
 If you go with the second route however, no need to show all your intermediate steps, just add the new files in one commit.</div>
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<p>Hi Alex,</p>
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<p>I suggested the approach in this patch series since to minimize code duplication and maintain readability of the code. I don't think it's very error prone. I believe this is more maintainable than a separate arcturus_ih.c. I'll have some more specific comments
 on Alejandro's patches.</p>
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<p>Regards,<br>
  Felix<br>
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Alex</div>
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<div id="x_x_divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" color="#000000" style="font-size:11pt"><b>From:</b> amd-gfx
<a class="x_x_moz-txt-link-rfc2396E" href="mailto:amd-gfx-bounces@lists.freedesktop.org">
<amd-gfx-bounces@lists.freedesktop.org></a> on behalf of Alex Sierra <a class="x_x_moz-txt-link-rfc2396E" href="mailto:alex.sierra@amd.com">
<alex.sierra@amd.com></a><br>
<b>Sent:</b> Thursday, March 19, 2020 8:22 PM<br>
<b>To:</b> <a class="x_x_moz-txt-link-abbreviated" href="mailto:amd-gfx@lists.freedesktop.org">
amd-gfx@lists.freedesktop.org</a> <a class="x_x_moz-txt-link-rfc2396E" href="mailto:amd-gfx@lists.freedesktop.org">
<amd-gfx@lists.freedesktop.org></a><br>
<b>Cc:</b> Sierra Guiza, Alejandro (Alex) <a class="x_x_moz-txt-link-rfc2396E" href="mailto:Alex.Sierra@amd.com">
<Alex.Sierra@amd.com></a><br>
<b>Subject:</b> [PATCH 1/4] drm/amdgpu: add stride to calculate oss ring offsets</font>
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<div class="x_x_PlainText">Arcturus and vega10 share the same vega10_ih, however both<br>
have different register offsets at the ih ring section.<br>
This variable is used to help calculate ih ring register addresses<br>
from the osssys, that corresponds to the current asic type.<br>
<br>
Signed-off-by: Alex Sierra <a class="x_x_moz-txt-link-rfc2396E" href="mailto:alex.sierra@amd.com">
<alex.sierra@amd.com></a><br>
---<br>
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 4 ++++<br>
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h | 1 +<br>
 2 files changed, 5 insertions(+)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c<br>
index 5ed4227f304b..fa384ae9a9bc 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c<br>
@@ -279,6 +279,10 @@ int amdgpu_irq_init(struct amdgpu_device *adev)<br>
                                 amdgpu_hotplug_work_func);<br>
         }<br>
 <br>
+       if (adev->asic_type == CHIP_ARCTURUS)<br>
+               adev->irq.ring_stride = 1;<br>
+       else<br>
+               adev->irq.ring_stride = 0;<br>
         INIT_WORK(&adev->irq.ih1_work, amdgpu_irq_handle_ih1);<br>
         INIT_WORK(&adev->irq.ih2_work, amdgpu_irq_handle_ih2);<br>
 <br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h<br>
index c718e94a55c9..1ec5b735cd9e 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h<br>
@@ -97,6 +97,7 @@ struct amdgpu_irq {<br>
         struct irq_domain               *domain; /* GPU irq controller domain */<br>
         unsigned                        virq[AMDGPU_MAX_IRQ_SRC_ID];<br>
         uint32_t                        srbm_soft_reset;<br>
+       unsigned                        ring_stride;<br>
 };<br>
 <br>
 void amdgpu_irq_disable_all(struct amdgpu_device *adev);<br>
-- <br>
2.17.1<br>
<br>
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