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[AMD Public Use]<br>
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While you are at it, can you clean up the local defines of these registers in</div>
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drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c</div>
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drivers/gpu/drm/amd/powerplay/smu_v12_0.c</div>
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drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c</div>
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and verify that the appropriate offset is used for both Renoir and raven?</div>
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Alex<br>
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<div id="divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" face="Calibri, sans-serif" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Tom St Denis <tom.stdenis@amd.com><br>
<b>Sent:</b> Wednesday, March 25, 2020 3:22 PM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> StDenis, Tom <Tom.StDenis@amd.com><br>
<b>Subject:</b> [PATCH] drm/amd/amdgpu: Fix SMUIO/PWR Confusion (v2)</font>
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<div class="PlainText">The PWR block was merged into the SMUIO block by revision 12 so we add<br>
that to the smuio_12_0_0 headers.<br>
<br>
(v2): Drop nonsensical smuio_10_0_0 header<br>
<br>
Signed-off-by: Tom St Denis <tom.stdenis@amd.com><br>
---<br>
.../gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h | 3 +++<br>
.../drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h | 5 +++++<br>
2 files changed, 8 insertions(+)<br>
<br>
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h<br>
index 327b4d09f66d..9bf73284ad73 100644<br>
--- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h<br>
+++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h<br>
@@ -24,4 +24,7 @@<br>
#define mmSMUIO_GFX_MISC_CNTL 0x00c8<br>
#define mmSMUIO_GFX_MISC_CNTL_BASE_IDX 0<br>
<br>
+#define mmPWR_MISC_CNTL_STATUS 0x0183<br>
+#define mmPWR_MISC_CNTL_STATUS_BASE_IDX 1<br>
+<br>
#endif<br>
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h<br>
index d815452cfd15..26556fa3d054 100644<br>
--- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h<br>
+++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h<br>
@@ -24,5 +24,10 @@<br>
//SMUIO_GFX_MISC_CNTL<br>
#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK 0x00000006L<br>
#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT 0x1<br>
+//PWR_MISC_CNTL_STATUS<br>
+#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0<br>
+#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1<br>
+#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L<br>
+#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L<br>
<br>
#endif<br>
-- <br>
2.25.1<br>
<br>
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