<div dir="auto">No, Mesa won't use it. It's only necessary for the constant engine. My understanding from various discussions with the PAL team is that they need it, but I don't know if they even understand what the MEM_SYNC flag does.<div dir="auto"><br></div><div dir="auto">Marek</div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Mon., Apr. 27, 2020, 10:53 Christian König, <<a href="mailto:ckoenig.leichtzumerken@gmail.com">ckoenig.leichtzumerken@gmail.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
  
    
  
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    <div>Yeah, but is Mesa going to use it?<br>
      <br>
      Christian.<br>
      <br>
      Am 27.04.20 um 15:54 schrieb Marek Olšák:<br>
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        <div>PAL requested it and they are going to use it. (it looks
          like they have to use it for correctness)<br>
        </div>
        <div><br>
        </div>
        <div>Marek<br>
        </div>
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      <br>
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        <div dir="ltr" class="gmail_attr">On Mon, Apr 27, 2020 at 9:02
          AM Deucher, Alexander <<a href="mailto:Alexander.Deucher@amd.com" target="_blank" rel="noreferrer">Alexander.Deucher@amd.com</a>>
          wrote:<br>
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            <p style="font-family:Arial;font-size:10pt;color:rgb(0,120,215);margin:15pt" align="Left">
              [AMD Official Use Only - Internal Distribution Only]<br>
            </p>
            <br>
            <div>
              <div style="font-family:Calibri,Arial,Helvetica,sans-serif;font-size:12pt;color:rgb(0,0,0)">Do
                we have open source code UMD code which uses this?</div>
              <div style="font-family:Calibri,Arial,Helvetica,sans-serif;font-size:12pt;color:rgb(0,0,0)"><br>
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              <div style="font-family:Calibri,Arial,Helvetica,sans-serif;font-size:12pt;color:rgb(0,0,0)">Alex<br>
              </div>
              <hr style="display:inline-block;width:98%">
              <div id="m_-6677784358645779172gmail-m_-4239586701017450887divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" face="Calibri,
                  sans-serif" color="#000000"><b>From:</b> Christian
                  König <<a href="mailto:ckoenig.leichtzumerken@gmail.com" target="_blank" rel="noreferrer">ckoenig.leichtzumerken@gmail.com</a>><br>
                  <b>Sent:</b> Sunday, April 26, 2020 4:55 AM<br>
                  <b>To:</b> Marek Olšák <<a href="mailto:maraeo@gmail.com" target="_blank" rel="noreferrer">maraeo@gmail.com</a>>;
                  Koenig, Christian <<a href="mailto:Christian.Koenig@amd.com" target="_blank" rel="noreferrer">Christian.Koenig@amd.com</a>><br>
                  <b>Cc:</b> Deucher, Alexander <<a href="mailto:Alexander.Deucher@amd.com" target="_blank" rel="noreferrer">Alexander.Deucher@amd.com</a>>;
                  amd-gfx mailing list <<a href="mailto:amd-gfx@lists.freedesktop.org" target="_blank" rel="noreferrer">amd-gfx@lists.freedesktop.org</a>><br>
                  <b>Subject:</b> Re: drm/amdgpu: apply
                  AMDGPU_IB_FLAG_EMIT_MEM_SYNC to compute IBs too</font>
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                <div>Thanks for that explanation. I suspected that there
                  was a good reason to have that in the kernel, but
                  couldn't find one.<br>
                  <br>
                  In this case the patch is Reviewed-by: Christian König
                  <a href="mailto:christian.koenig@amd.com" target="_blank" rel="noreferrer">
                    <christian.koenig@amd.com></a><br>
                  <br>
                  We should probably add this explanation as comment to
                  the flag as well.<br>
                  <br>
                  Thanks,<br>
                  Christian.<br>
                  <br>
                  Am 26.04.20 um 02:43 schrieb Marek Olšák:<br>
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                  <div dir="auto">It was merged into
                    amd-staging-drm-next.
                    <div dir="auto"><br>
                    </div>
                    <div dir="auto">I'm not absolutely sure, but I think
                      we need to invalidate before IBs if an IB is
                      cached in L2 and the CPU has updated it. It can
                      only be cached in L2 if something other than CP
                      has read it or written to it without invalidation.
                      CP reads don't cache it but they can hit the cache
                      if it's already cached.</div>
                    <div dir="auto"><br>
                    </div>
                    <div dir="auto">For CE, we need to invalidate before
                      the IB in the kernel, because CE IBs can't do
                      cache invalidations IIRC. This is the number one
                      reason for merging the already pushed commits.</div>
                    <div dir="auto"><br>
                    </div>
                    <div dir="auto">Marek</div>
                  </div>
                  <br>
                  <div>
                    <div dir="ltr">On Sat., Apr. 25, 2020, 11:03
                      Christian König, <<a href="mailto:ckoenig.leichtzumerken@gmail.com" target="_blank" rel="noreferrer">ckoenig.leichtzumerken@gmail.com</a>>
                      wrote:<br>
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                        <div>Was that patch set actually merged
                          upstream? My last status is that we couldn't
                          find a reason why we need to do this in the
                          kernel.<br>
                          <br>
                          Christian.<br>
                          <br>
                          Am 25.04.20 um 10:52 schrieb Marek Olšák:<br>
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                          <div dir="ltr">
                            <div>This was missed.</div>
                            <div><br>
                            </div>
                            <div>Marek<br>
                            </div>
                          </div>
                          <br>
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      <pre>_______________________________________________
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