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<p class="MsoNormal">Here is the reason we should always insert a “sync mem” packet at the FENCE place of SDMA, not before IB emit.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">By always inserting “sync mem” in the FENCE place we can make sure:1<o:p></o:p></p>
<ol style="margin-top:0in" start="1" type="1">
<li class="MsoListParagraph" style="margin-left:0in;mso-list:l0 level1 lfo1">data is really flushed to system memory before CPU try to read it
<o:p></o:p></li><li class="MsoListParagraph" style="margin-left:0in;mso-list:l0 level1 lfo1">all the G2LC is invalidated by “sync mem”, thus in the next round SDMA IB, it won’t get staled data from G2LC cache
<o:p></o:p></li></ol>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">by inserting “sync mem” in prior to IB could only achieve : Avoid get staled data in g2lc during IB execution
<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">for GFX/COMPUTE ring since they have release_mem packet so it is inherently doing the G2LC flush and invalidate upon a fence signaled
<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">_____________________________________<o:p></o:p></p>
<p class="MsoNormal"><span style="font-size:12.0pt;color:black;background:white">Monk Liu|GPU Virtualization Team |</span><span style="font-size:12.0pt;color:#C82613;border:none windowtext 1.0pt;padding:0in;background:white">AMD<o:p></o:p></span></p>
<p class="MsoNormal"><img width="80" height="80" style="width:.8333in;height:.8333in" id="_x0000_i1026" src="cid:image001.png@01D61E4C.901A7890" alt="sig-cloud-gpu"><o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><b>From:</b> Liu, Monk <br>
<b>Sent:</b> Wednesday, April 29, 2020 5:06 PM<br>
<b>To:</b> 'Marek Olšák' <maraeo@gmail.com>; amd-gfx mailing list <amd-gfx@lists.freedesktop.org>; Koenig, Christian <Christian.Koenig@amd.com><br>
<b>Subject:</b> RE: drm/amdgpu: invalidate L2 before SDMA IBs (on gfx10)<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Hi <a id="OWAAM709EE8E0E6054CD48698E878A98E9795" href="mailto:Christian.Koenig@amd.com">
<span style="font-family:"Calibri",sans-serif;text-decoration:none">@Koenig, Christian</span></a> & Marek<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I still have some concerns regarding Marek’s patch, correct me if I’m wrong<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">See that Marek put a SDMA_OP_GCR_REQ before emitting IB, to make sure SDMA won’t get stale cache data during the IB execution.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">But that “SDMA_OP_GCR_REQ” only invalidate/flush the GFXHUB’s G2LC cache right ? what if the memory is changed by MM or CPU (out side of GFXHUB) ?<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Can this “ SDMA_OP_GCR_REQ” force MMHUB or even CPU to flush their operation result from their cache to memory ??<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Besides, with my understanding the “EOP” of gfx ring is doing the thing of “invalidate/flush” L2 cache upon a fence signaled, so what we should do on SDMA5 is to insert this “SDMA_OP_GCR_REQ”<o:p></o:p></p>
<p class="MsoNormal">Right before thee “emit_fence” of SDMA (this is what windows KMD do)<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">thanks <o:p></o:p></p>
<p class="MsoNormal">_____________________________________<o:p></o:p></p>
<p class="MsoNormal"><span style="font-size:12.0pt;color:black;background:white">Monk Liu|GPU Virtualization Team |</span><span style="font-size:12.0pt;color:#C82613;border:none windowtext 1.0pt;padding:0in;background:white">AMD<o:p></o:p></span></p>
<p class="MsoNormal"><img border="0" width="80" height="80" style="width:.8333in;height:.8333in" id="Picture_x0020_1" src="cid:image001.png@01D61E4C.901A7890" alt="sig-cloud-gpu"><o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><b>From:</b> amd-gfx <<a href="mailto:amd-gfx-bounces@lists.freedesktop.org">amd-gfx-bounces@lists.freedesktop.org</a>>
<b>On Behalf Of </b>Marek Ol?ák<br>
<b>Sent:</b> Saturday, April 25, 2020 4:52 PM<br>
<b>To:</b> amd-gfx mailing list <<a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a>><br>
<b>Subject:</b> drm/amdgpu: invalidate L2 before SDMA IBs (on gfx10)<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">This should fix SDMA hangs on gfx10.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Marek<o:p></o:p></p>
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