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[AMD Public Use]<br>
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Acked-by: Alex Deucher <alexander.deucher@amd.com><br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Yintian Tao <yttao@amd.com><br>
<b>Sent:</b> Tuesday, May 12, 2020 6:17 AM<br>
<b>To:</b> Deucher, Alexander <Alexander.Deucher@amd.com>; Liu, Monk <Monk.Liu@amd.com>; Liu, Shaoyun <Shaoyun.Liu@amd.com><br>
<b>Cc:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>; Tao, Yintian <Yintian.Tao@amd.com><br>
<b>Subject:</b> [PATCH] drm/amdgpu: turn back rlcg write for gfx_v10</font>
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<div class="PlainText">There is no need to use amdgpu_mm_wreg_mmio_rlc()<br>
during initialization time because this interface<br>
is only designed for debugfs case to access the<br>
registers which are only permitted by RLCG during<br>
run-time. Therefore, turn back rlcg write for gfx_v10.<br>
If we not turn back it, it will raise amdgpu load failure.<br>
[ 54.904333] amdgpu: SMU driver if version not matched<br>
[ 54.904393] amdgpu: SMU is initialized successfully!<br>
[ 54.905971] [drm] kiq ring mec 2 pipe 1 q 0<br>
[ 55.115416] amdgpu 0000:00:06.0: [drm:amdgpu_ring_test_helper [amdgpu]] *ERROR* ring gfx_0.0.0 test failed (-110)<br>
[ 55.118877] [drm:amdgpu_device_init [amdgpu]] *ERROR* hw_init of IP block <gfx_v10_0> failed -110<br>
[ 55.126587] amdgpu 0000:00:06.0: amdgpu_device_ip_init failed<br>
[ 55.133466] amdgpu 0000:00:06.0: Fatal error during GPU init<br>
<br>
Signed-off-by: Yintian Tao <yttao@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 14 ++++++--------<br>
1 file changed, 6 insertions(+), 8 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c<br>
index 449408cfd018..bd5dd4f64311 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c<br>
@@ -4577,13 +4577,11 @@ static int gfx_v10_0_init_csb(struct amdgpu_device *adev)<br>
adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);<br>
<br>
/* csib */<br>
- /* amdgpu_mm_wreg_mmio_rlc will fall back to mmio if doesn't support rlcg_write */<br>
- amdgpu_mm_wreg_mmio_rlc(adev, SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),<br>
- adev->gfx.rlc.clear_state_gpu_addr >> 32, 0);<br>
- amdgpu_mm_wreg_mmio_rlc(adev, SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),<br>
- adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc, 0);<br>
- amdgpu_mm_wreg_mmio_rlc(adev, SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),<br>
- adev->gfx.rlc.clear_state_size, 0);<br>
+ WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,<br>
+ adev->gfx.rlc.clear_state_gpu_addr >> 32);<br>
+ WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,<br>
+ adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);<br>
+ WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);<br>
<br>
return 0;<br>
}<br>
@@ -5192,7 +5190,7 @@ static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)<br>
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);<br>
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);<br>
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);<br>
- amdgpu_mm_wreg_mmio_rlc(adev, SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL), tmp, 0);<br>
+ WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);<br>
<br>
for (i = 0; i < adev->usec_timeout; i++) {<br>
if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)<br>
-- <br>
2.17.1<br>
<br>
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