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[AMD Public Use]<br>
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Series is:</div>
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Reviewed-by: Alex Deucher <alexander.deucher@amd.com><br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Nirmoy Das <nirmoy.aiemd@gmail.com><br>
<b>Sent:</b> Thursday, June 18, 2020 9:17 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Das, Nirmoy <Nirmoy.Das@amd.com><br>
<b>Subject:</b> [PATCH 1/4] drm/amdgpu: label internally used symbols as static</font>
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<div class="PlainText">Used sparse(make C=1) to find these loose ends.<br>
<br>
Signed-off-by: Nirmoy Das <nirmoy.das@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 2 +-<br>
drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c | 4 ++--<br>
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-<br>
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 +++---<br>
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 4 ++--<br>
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 4 ++--<br>
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 4 ++--<br>
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +-<br>
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +-<br>
9 files changed, 15 insertions(+), 15 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c<br>
index b5d6274952a5..4ef38c2411ae 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c<br>
@@ -32,7 +32,7 @@<br>
#define mmMM_DATA 0x1<br>
#define HW_ID_MAX 300<br>
<br>
-const char *hw_id_names[HW_ID_MAX] = {<br>
+static const char *hw_id_names[HW_ID_MAX] = {<br>
[MP1_HWID] = "MP1",<br>
[MP2_HWID] = "MP2",<br>
[THM_HWID] = "THM",<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c<br>
index 6ae80b33182c..e811fecc540f 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c<br>
@@ -32,7 +32,7 @@<br>
#define I2C_PRODUCT_INFO_ADDR_SIZE 0x2<br>
#define I2C_PRODUCT_INFO_OFFSET 0xC0<br>
<br>
-bool is_fru_eeprom_supported(struct amdgpu_device *adev)<br>
+static bool is_fru_eeprom_supported(struct amdgpu_device *adev)<br>
{<br>
/* TODO: Gaming SKUs don't have the FRU EEPROM.<br>
* Use this hack to address hangs on modprobe on gaming SKUs<br>
@@ -48,7 +48,7 @@ bool is_fru_eeprom_supported(struct amdgpu_device *adev)<br>
return false;<br>
}<br>
<br>
-int amdgpu_fru_read_eeprom(struct amdgpu_device *adev, uint32_t addrptr,<br>
+static int amdgpu_fru_read_eeprom(struct amdgpu_device *adev, uint32_t addrptr,<br>
unsigned char *buff)<br>
{<br>
int ret, size;<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c<br>
index 60558497f054..0723dee2958b 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c<br>
@@ -583,7 +583,7 @@ static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,<br>
cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;<br>
}<br>
<br>
-int psp_ta_invoke(struct psp_context *psp,<br>
+static int psp_ta_invoke(struct psp_context *psp,<br>
uint32_t ta_cmd_id,<br>
uint32_t session_id)<br>
{<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c<br>
index 9bfe59b70030..ab8e7c91c645 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c<br>
@@ -86,7 +86,7 @@ void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)<br>
amdgpu_ras_get_context(adev)->error_query_ready = ready;<br>
}<br>
<br>
-bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)<br>
+static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)<br>
{<br>
if (adev && amdgpu_ras_get_context(adev))<br>
return amdgpu_ras_get_context(adev)->error_query_ready;<br>
@@ -505,7 +505,7 @@ struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,<br>
}<br>
/* obj end */<br>
<br>
-void amdgpu_ras_parse_status_code(struct amdgpu_device* adev,<br>
+static void amdgpu_ras_parse_status_code(struct amdgpu_device *adev,<br>
const char* invoke_type,<br>
const char* block_name,<br>
enum ta_ras_status ret)<br>
@@ -815,7 +815,7 @@ int amdgpu_ras_error_query(struct amdgpu_device *adev,<br>
}<br>
<br>
/* Trigger XGMI/WAFL error */<br>
-int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev,<br>
+static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev,<br>
struct ta_ras_trigger_error_input *block_info)<br>
{<br>
int ret;<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c<br>
index 5b42c50366c9..64b572307104 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c<br>
@@ -1113,7 +1113,7 @@ static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)<br>
#endif<br>
}<br>
<br>
-int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,<br>
+static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,<br>
struct ttm_buffer_object *tbo,<br>
uint64_t flags)<br>
{<br>
@@ -1835,7 +1835,7 @@ static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev)<br>
(adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);<br>
ctx->train_data_size =<br>
GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;<br>
- <br>
+<br>
DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",<br>
ctx->train_data_size,<br>
ctx->p2c_train_data_offset,<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c<br>
index 0891f27ba166..da233a9e429d 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c<br>
@@ -515,12 +515,12 @@ void amdgpu_detect_virtualization(struct amdgpu_device *adev)<br>
}<br>
}<br>
<br>
-bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev)<br>
+static bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev)<br>
{<br>
return amdgpu_sriov_is_debug(adev) ? true : false;<br>
}<br>
<br>
-bool amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device *adev)<br>
+static bool amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device *adev)<br>
{<br>
return amdgpu_sriov_is_normal(adev) ? true : false;<br>
}<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c<br>
index 0cc011f9190d..4aec76049a60 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c<br>
@@ -3039,7 +3039,7 @@ static void gfx_v7_0_mqd_init(struct amdgpu_device *adev,<br>
mqd->cp_hqd_active = 1;<br>
}<br>
<br>
-int gfx_v7_0_mqd_commit(struct amdgpu_device *adev, struct cik_mqd *mqd)<br>
+static int gfx_v7_0_mqd_commit(struct amdgpu_device *adev, struct cik_mqd *mqd)<br>
{<br>
uint32_t tmp;<br>
uint32_t mqd_reg;<br>
@@ -5209,7 +5209,7 @@ static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)<br>
cu_info->lds_size = 64;<br>
}<br>
<br>
-const struct amdgpu_ip_block_version gfx_v7_0_ip_block =<br>
+static const struct amdgpu_ip_block_version gfx_v7_0_ip_block =<br>
{<br>
.type = AMD_IP_BLOCK_TYPE_GFX,<br>
.major = 7,<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c<br>
index 1d4128227ffd..efb759b62d21 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c<br>
@@ -4589,7 +4589,7 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)<br>
return 0;<br>
}<br>
<br>
-int gfx_v8_0_mqd_commit(struct amdgpu_device *adev,<br>
+static int gfx_v8_0_mqd_commit(struct amdgpu_device *adev,<br>
struct vi_mqd *mqd)<br>
{<br>
uint32_t mqd_reg;<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c<br>
index c3e59b765268..99ffc3e1fddc 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c<br>
@@ -722,7 +722,7 @@ static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =<br>
mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0,<br>
};<br>
<br>
-void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v)<br>
+static void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v)<br>
{<br>
static void *scratch_reg0;<br>
static void *scratch_reg1;<br>
-- <br>
2.27.0<br>
<br>
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