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[AMD Public Use]<br>
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Hi Alex,</div>
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amdgpu_gfx_off_ctrl() invoked by a few other functions, like amdgpu_info_ioctl() ,</div>
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putting the code into amdgpu_gfx_off_ctrl() will cost more meaningless time on SPM golden reconfiguration.</div>
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<i><span style="color: rgb(23, 78, 134);">amdgpu_gfx_off_ctrl(adev, false);</span></i>
<div><i><span style="color: rgb(23, 78, 134);">amdgpu_asic_read_register(adev, se_num, sh_num, info->read_mmr_reg.dword_offset + i, ®s[i])</span><span style="color: rgb(23, 78, 134);">;</span><span><br>
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<div><i><span style="color: rgb(23, 78, 134);">amdgpu_gfx_off_ctrl(adev, true);</span></i>
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In most cases, we don't care about the SPM, so I think smu_enable_umd_pstate is a better place.</div>
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Thanks very much!<br>
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Rico<br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Deucher, Alexander <Alexander.Deucher@amd.com><br>
<b>Sent:</b> Tuesday, July 28, 2020 22:16<br>
<b>To:</b> Yin, Tianci (Rico) <Tianci.Yin@amd.com>; amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Tuikov, Luben <Luben.Tuikov@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; Xu, Feifei <Feifei.Xu@amd.com>; Hesik, Christopher <Christopher.Hesik@amd.com>; Swamy, Manjunatha <Manjunatha.Swamy@amd.com>; Quan, Evan <Evan.Quan@amd.com>; Chen, Guchun
<Guchun.Chen@amd.com>; Feng, Kenneth <Kenneth.Feng@amd.com><br>
<b>Subject:</b> Re: [PATCH] drm/amdgpu: reconfigure spm golden settings on Navi1x after GFXOFF exit(v2)</font>
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[AMD Public Use]<br>
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Would it be better to put this code into amdgpu_gfx_off_ctrl()? Then we'll handle this in all cases where we disable gfx off.</div>
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Alex</div>
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<div id="x_divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" color="#000000" style="font-size:11pt"><b>From:</b> Tianci Yin <tianci.yin@amd.com><br>
<b>Sent:</b> Tuesday, July 28, 2020 3:04 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Tuikov, Luben <Luben.Tuikov@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; Xu, Feifei <Feifei.Xu@amd.com>; Hesik, Christopher <Christopher.Hesik@amd.com>; Swamy, Manjunatha <Manjunatha.Swamy@amd.com>;
Quan, Evan <Evan.Quan@amd.com>; Chen, Guchun <Guchun.Chen@amd.com>; Feng, Kenneth <Kenneth.Feng@amd.com>; Yin, Tianci (Rico) <Tianci.Yin@amd.com><br>
<b>Subject:</b> [PATCH] drm/amdgpu: reconfigure spm golden settings on Navi1x after GFXOFF exit(v2)</font>
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<div class="x_PlainText">From: "Tianci.Yin" <tianci.yin@amd.com><br>
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On Navi1x, the SPM golden settings will be lost after GFXOFF enter/exit,<br>
reconfigure the golden settings after GFXOFF exit.<br>
<br>
Change-Id: I9358ba9c65f241c36f8a35916170b19535148ee9<br>
Reviewed-by: Feifei Xu <Feifei Xu@amd.com><br>
Signed-off-by: Tianci.Yin <tianci.yin@amd.com><br>
---<br>
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 19 +++++++++++++++----<br>
1 file changed, 15 insertions(+), 4 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c<br>
index 55463e7a11e2..41487123c207 100644<br>
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c<br>
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c<br>
@@ -1309,6 +1309,7 @@ static int smu_enable_umd_pstate(void *handle,<br>
<br>
struct smu_context *smu = (struct smu_context*)(handle);<br>
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);<br>
+ struct amdgpu_device *adev = smu->adev;<br>
<br>
if (!smu->is_apu && !smu_dpm_ctx->dpm_context)<br>
return -EINVAL;<br>
@@ -1318,12 +1319,22 @@ static int smu_enable_umd_pstate(void *handle,<br>
if (*level & profile_mode_mask) {<br>
smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;<br>
smu_dpm_ctx->enable_umd_pstate = true;<br>
- amdgpu_device_ip_set_powergating_state(smu->adev,<br>
+ amdgpu_device_ip_set_powergating_state(adev,<br>
AMD_IP_BLOCK_TYPE_GFX,<br>
AMD_PG_STATE_UNGATE);<br>
- amdgpu_device_ip_set_clockgating_state(smu->adev,<br>
+ amdgpu_device_ip_set_clockgating_state(adev,<br>
AMD_IP_BLOCK_TYPE_GFX,<br>
AMD_CG_STATE_UNGATE);<br>
+<br>
+ if (adev->asic_type >= CHIP_NAVI10 &&<br>
+ adev->asic_type <= CHIP_NAVI12 &&<br>
+ (adev->pm.pp_feature & PP_GFXOFF_MASK)) {<br>
+ if (adev->gfx.funcs->init_spm_golden) {<br>
+ dev_dbg(adev->dev,"GFXOFF exited, re-init SPM golden settings\n");<br>
+ amdgpu_gfx_init_spm_golden(adev);<br>
+ } else<br>
+ dev_warn(adev->dev,"Callback init_spm_golden is NULL\n");<br>
+ }<br>
}<br>
} else {<br>
/* exit umd pstate, restore level, enable gfx cg*/<br>
@@ -1331,10 +1342,10 @@ static int smu_enable_umd_pstate(void *handle,<br>
if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)<br>
*level = smu_dpm_ctx->saved_dpm_level;<br>
smu_dpm_ctx->enable_umd_pstate = false;<br>
- amdgpu_device_ip_set_clockgating_state(smu->adev,<br>
+ amdgpu_device_ip_set_clockgating_state(adev,<br>
AMD_IP_BLOCK_TYPE_GFX,<br>
AMD_CG_STATE_GATE);<br>
- amdgpu_device_ip_set_powergating_state(smu->adev,<br>
+ amdgpu_device_ip_set_powergating_state(adev,<br>
AMD_IP_BLOCK_TYPE_GFX,<br>
AMD_PG_STATE_GATE);<br>
}<br>
-- <br>
2.17.1<br>
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