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[AMD Official Use Only - Internal Distribution Only]<br>
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Acked-by: Alex Deucher <alexander.deucher@amd.com><br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Quan, Evan <Evan.Quan@amd.com><br>
<b>Sent:</b> Friday, August 7, 2020 5:31 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Deucher, Alexander <Alexander.Deucher@amd.com>; Quan, Evan <Evan.Quan@amd.com><br>
<b>Subject:</b> [PATCH] drm/amd/powerplay: correct UVD/VCE PG state on custom pptable uploading</font>
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<div class="PlainText">The UVD/VCE PG state is managed by UVD and VCE IP. It's error-prone to<br>
assume the bootup state in SMU based on the dpm status.<br>
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Change-Id: Ib88298ab9812d7d242592bcd55eea140bef6696a<br>
Signed-off-by: Evan Quan <evan.quan@amd.com><br>
---<br>
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 6 ------<br>
1 file changed, 6 deletions(-)<br>
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diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c<br>
index acc926c20c55..da84012b7fd5 100644<br>
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c<br>
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c<br>
@@ -1645,12 +1645,6 @@ static void vega20_init_powergate_state(struct pp_hwmgr *hwmgr)<br>
<br>
data->uvd_power_gated = true;<br>
data->vce_power_gated = true;<br>
-<br>
- if (data->smu_features[GNLD_DPM_UVD].enabled)<br>
- data->uvd_power_gated = false;<br>
-<br>
- if (data->smu_features[GNLD_DPM_VCE].enabled)<br>
- data->vce_power_gated = false;<br>
}<br>
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static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)<br>
-- <br>
2.28.0<br>
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