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[AMD Official Use Only - Internal Distribution Only]<br>
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You can probably just squash patches 2-5 into one patch. Either way, series is:</div>
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Reviewed-by: Alex Deucher <alexander.deucher@amd.com><br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Quan, Evan <Evan.Quan@amd.com><br>
<b>Sent:</b> Monday, August 17, 2020 3:49 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Deucher, Alexander <Alexander.Deucher@amd.com>; Quan, Evan <Evan.Quan@amd.com><br>
<b>Subject:</b> [PATCH 1/5] drm/amd/pm: disable/enable gfx ulv on UMD pstate enter/exit</font>
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<div class="PlainText">Add gfx ulv disablement/enablement on UMD pstate entering/exiting.<br>
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Change-Id: Ieb38fdb5975b563f24c0b172fedd01acf99afb10<br>
Signed-off-by: Evan Quan <evan.quan@amd.com><br>
---<br>
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 1 +<br>
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 ++<br>
drivers/gpu/drm/amd/pm/swsmu/smu_internal.h | 1 +<br>
3 files changed, 4 insertions(+)<br>
<br>
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h<br>
index bbe4a343e9f1..7cc707ec21c3 100644<br>
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h<br>
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h<br>
@@ -596,6 +596,7 @@ struct pptable_funcs {<br>
int (*set_pp_feature_mask)(struct smu_context *smu, uint64_t new_mask);<br>
ssize_t (*get_gpu_metrics)(struct smu_context *smu, void **table);<br>
int (*enable_mgpu_fan_boost)(struct smu_context *smu);<br>
+ int (*gfx_ulv_control)(struct smu_context *smu, bool enablement);<br>
};<br>
<br>
typedef enum {<br>
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c<br>
index 7d17c4f1b489..221b5c923ce1 100644<br>
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c<br>
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c<br>
@@ -1440,6 +1440,7 @@ static int smu_enable_umd_pstate(void *handle,<br>
amdgpu_device_ip_set_clockgating_state(smu->adev,<br>
AMD_IP_BLOCK_TYPE_GFX,<br>
AMD_CG_STATE_UNGATE);<br>
+ smu_gfx_ulv_control(smu, false);<br>
}<br>
} else {<br>
/* exit umd pstate, restore level, enable gfx cg*/<br>
@@ -1447,6 +1448,7 @@ static int smu_enable_umd_pstate(void *handle,<br>
if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)<br>
*level = smu_dpm_ctx->saved_dpm_level;<br>
smu_dpm_ctx->enable_umd_pstate = false;<br>
+ smu_gfx_ulv_control(smu, true);<br>
amdgpu_device_ip_set_clockgating_state(smu->adev,<br>
AMD_IP_BLOCK_TYPE_GFX,<br>
AMD_CG_STATE_GATE);<br>
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h<br>
index 264073d4e263..2fe29c6a00ce 100644<br>
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h<br>
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h<br>
@@ -92,6 +92,7 @@<br>
#define smu_get_asic_power_limits(smu) smu_ppt_funcs(get_power_limit, 0, smu)<br>
#define smu_get_pp_feature_mask(smu, buf) smu_ppt_funcs(get_pp_feature_mask, 0, smu, buf)<br>
#define smu_set_pp_feature_mask(smu, new_mask) smu_ppt_funcs(set_pp_feature_mask, 0, smu, new_mask)<br>
+#define smu_gfx_ulv_control(smu, enablement) smu_ppt_funcs(gfx_ulv_control, 0, smu, enablement)<br>
<br>
#endif<br>
#endif<br>
-- <br>
2.28.0<br>
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