<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns:m="http://schemas.microsoft.com/office/2004/12/omml" xmlns="http://www.w3.org/TR/REC-html40"> <head> <meta http-equiv="Content-Type" content="text/html; charset=us-ascii"> <meta name="Generator" content="Microsoft Word 15 (filtered medium)"> <style></style> </head> <body lang="EN-US" link="blue" vlink="purple"> [AMD Public Use] <div> <div class="WordSection1"> [AMD Public Use]<o:p></o:p> <o:p> </o:p> Hi <a id="OWAAM758C783C88E142F8A5D7099ED10A66B1" href="mailto:JingWen.Chen2@amd.com"> @Chen, JingWen</a>,<o:p></o:p> <o:p> </o:p> CAP firmware will be only used for SRIOV. So please just add specific code path under SRIOV to initialize that firmware. Do not introduce SRIOV specific code for the most PSP firmware you are not used in guest.<o:p></o:p> <o:p> </o:p> Regards, Hawking<o:p></o:p> <o:p> </o:p> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in"> From: Chen, JingWen <JingWen.Chen2@amd.com> Sent: Tuesday, September 22, 2020 18:27 To: Deng, Emily <Emily.Deng@amd.com>; Wang, Kevin(Yang) <Kevin1.Wang@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; amd-gfx@lists.freedesktop.org Subject: RE: [PATCH 2/2] drm/amd: Skip not used microcode loading in SRIOV<o:p></o:p> </div> </div> <o:p> </o:p> [AMD Public Use]<o:p></o:p> <o:p> </o:p> <div> [AMD Public Use]<o:p></o:p> <o:p> </o:p> Hi Hawking,<o:p></o:p> <o:p> </o:p> We may need other features in PSP in the future, e.g. load cap fw. So we can’t skip the whole psp_init_microcode.<o:p></o:p> <o:p> </o:p> <div> Best Regards,<o:p></o:p> JingWen Chen<o:p></o:p> </div> <o:p> </o:p> <div style="border:none;border-left:solid blue 1.5pt;padding:0in 0in 0in 4.0pt"> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in"> From: Deng, Emily <<a href="mailto:Emily.Deng@amd.com">Emily.Deng@amd.com</a>> Sent: Tuesday, September 22, 2020 6:22 PM To: Wang, Kevin(Yang) <<a href="mailto:Kevin1.Wang@amd.com">Kevin1.Wang@amd.com</a>>; Zhang, Hawking <<a href="mailto:Hawking.Zhang@amd.com">Hawking.Zhang@amd.com</a>>; Chen, JingWen <<a href="mailto:JingWen.Chen2@amd.com">JingWen.Chen2@amd.com</a>>; <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a> Subject: RE: [PATCH 2/2] drm/amd: Skip not used microcode loading in SRIOV<o:p></o:p> </div> </div> <o:p> </o:p> [AMD Public Use]<o:p></o:p> <o:p> </o:p> <div> Hi Kevin and Hawking,<o:p></o:p> I think both you are right. But currently we haven’t good method to handle this. It seems need to re-arch the whole driver, not only refer to this patch. Only refer to this patch, I think it is OK.<o:p></o:p> <o:p> </o:p> Best wishes<o:p></o:p> Emily Deng<o:p></o:p> <div style="border:none;border-left:solid blue 1.5pt;padding:0in 0in 0in 4.0pt"> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in"> From: amd-gfx <<a href="mailto:amd-gfx-bounces@lists.freedesktop.org">amd-gfx-bounces@lists.freedesktop.org</a>> On Behalf Of Wang, Kevin(Yang) Sent: Tuesday, September 22, 2020 3:38 PM To: Zhang, Hawking <<a href="mailto:Hawking.Zhang@amd.com">Hawking.Zhang@amd.com</a>>; Chen, JingWen <<a href="mailto:JingWen.Chen2@amd.com">JingWen.Chen2@amd.com</a>>; <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a> Subject: Re: [PATCH 2/2] drm/amd: Skip not used microcode loading in SRIOV<o:p></o:p> </div> </div> <o:p> </o:p> [AMD Public Use]<o:p></o:p> <o:p> </o:p> <div> [AMD Public Use]<o:p></o:p> <o:p> </o:p> <div> <div> Embedding these SRIOV check into the underlying functions is in many places, which is not conducive to subsequent code optimization and maintenance.<o:p></o:p> </div> <div> <div> It took a long time to clean up the SMU code before, but now some new checks have been introduced into the SMU code. <o:p></o:p> </div> <div> I think a new method should be adopted to solve this problem unless there's a special reason.<o:p></o:p> </div> <div> <o:p> </o:p> </div> <div> Best Regards, Kevin<o:p></o:p> </div> </div> <div class="MsoNormal" align="center" style="text-align:center"> <hr size="2" width="98%" align="center"> </div> <div id="divRplyFwdMsg"> From: amd-gfx <<a href="mailto:amd-gfx-bounces@lists.freedesktop.org">amd-gfx-bounces@lists.freedesktop.org</a>> on behalf of Zhang, Hawking <<a href="mailto:Hawking.Zhang@amd.com">Hawking.Zhang@amd.com</a>> Sent: Tuesday, September 22, 2020 3:25 PM To: Chen, JingWen <<a href="mailto:JingWen.Chen2@amd.com">JingWen.Chen2@amd.com</a>>; <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a> <<a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a>> Cc: Chen, JingWen <<a href="mailto:JingWen.Chen2@amd.com">JingWen.Chen2@amd.com</a>> Subject: RE: [PATCH 2/2] drm/amd: Skip not used microcode loading in SRIOV <o:p></o:p> <div> <o:p></o:p> </div> </div> <div> <div> [AMD Public Use] 1. Please do not add the amdgpu_sriov_vf check in every psp fw init_microcode function. psp_init_microcode is the entry point for all kinds of psp fw microcode initialization. 2. I'd like to get a whole picture on all the sequence you want to skip from guest side so that we can have more organized/reasonable approach to exclude those programing sequence for SRIOV, instead of having the amdgpu_sriov_vf patched case by case... Regards, Hawking -----Original Message----- From: amd-gfx <<a href="mailto:amd-gfx-bounces@lists.freedesktop.org">amd-gfx-bounces@lists.freedesktop.org</a>> On Behalf Of Jingwen Chen Sent: Tuesday, September 22, 2020 15:09 To: <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a> Cc: Chen, JingWen <<a href="mailto:JingWen.Chen2@amd.com">JingWen.Chen2@amd.com</a>> Subject: [PATCH 2/2] drm/amd: Skip not used microcode loading in SRIOV smc, sdma, sos, ta and asd fw is not used in SRIOV. Skip them to accelerate sw_init for navi12. v2: skip above fw in SRIOV for vega10 and sienna_cichlid Signed-off-by: Jingwen Chen <<a href="mailto:Jingwen.Chen2@amd.com">Jingwen.Chen2@amd.com</a>> --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 9 +++++++++ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 3 +++ drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 3 +++ drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 3 +++ .../gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c | 12 +++++++----- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 11 +++++++---- 6 files changed, 32 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 2c66e20b2ed9..9e2038de6ea7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -2385,6 +2385,9 @@ int psp_init_asd_microcode(struct psp_context *psp, const struct psp_firmware_header_v1_0 *asd_hdr; int err = 0; + if (amdgpu_sriov_vf(adev)) + return 0; + if (!chip_name) { dev_err(adev->dev, "invalid chip name for asd microcode\n"); return -EINVAL; @@ -2424,6 +2427,9 @@ int psp_init_sos_microcode(struct psp_context *psp, const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; int err = 0; + if (amdgpu_sriov_vf(adev)) + return 0; + if (!chip_name) { dev_err(adev->dev, "invalid chip name for sos microcode\n"); return -EINVAL; @@ -2558,6 +2564,9 @@ int psp_init_ta_microcode(struct psp_context *psp, int err = 0; int ta_index = 0; + if (amdgpu_sriov_vf(adev)) + return 0; + if (!chip_name) { dev_err(adev->dev, "invalid chip name for ta microcode\n"); return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 810635cbf4c1..86fb1eddf5a6 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -592,6 +592,9 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) struct amdgpu_firmware_info *info = NULL; const struct common_firmware_header *header = NULL; + if (amdgpu_sriov_vf(adev)) + return 0; + DRM_DEBUG("\n"); switch (adev->asic_type) { diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index 48c95a78a173..9c72b95b7463 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -203,6 +203,9 @@ static int sdma_v5_0_init_microcode(struct amdgpu_device *adev) const struct common_firmware_header *header = NULL; const struct sdma_firmware_header_v1_0 *hdr; + if (amdgpu_sriov_vf(adev)) + return 0; + DRM_DEBUG("\n"); switch (adev->asic_type) { diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index 34ccf376ee45..9f3952723c63 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -148,6 +148,9 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev) struct amdgpu_firmware_info *info = NULL; const struct common_firmware_header *header = NULL; + if (amdgpu_sriov_vf(adev)) + return 0; + DRM_DEBUG("\n"); switch (adev->asic_type) { diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c b/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c index 1e222c5d91a4..daf122f24f23 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c @@ -209,11 +209,13 @@ static int vega10_smu_init(struct pp_hwmgr *hwmgr) int ret; struct cgs_firmware_info info = {0}; - ret = cgs_get_firmware_info(hwmgr->device, - CGS_UCODE_ID_SMU, - &info); - if (ret || !info.kptr) - return -EINVAL; + if (!amdgpu_sriov_vf((struct amdgpu_device *)hwmgr->adev)) { + ret = cgs_get_firmware_info(hwmgr->device, + CGS_UCODE_ID_SMU, + &info); + if (ret || !info.kptr) + return -EINVAL; + } priv = kzalloc(sizeof(struct vega10_smumgr), GFP_KERNEL); diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 538e6f5e19eb..3010cb31324a 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -832,10 +832,13 @@ static int smu_sw_init(void *handle) smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; - ret = smu_init_microcode(smu); - if (ret) { - dev_err(adev->dev, "Failed to load smu firmware!\n"); - return ret; + + if (!amdgpu_sriov_vf(adev)) { + ret = smu_init_microcode(smu); + if (ret) { + dev_err(adev->dev, "Failed to load smu firmware!\n"); + return ret; + } } ret = smu_smc_table_sw_init(smu); -- 2.25.1 _______________________________________________ amd-gfx mailing list <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a> <a href="https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7CEmily.Deng%40amd.com%7C849a249868ba4128962408d85eca6667%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637363570681227058&sdata=ulesiZTX8RCcr4IQRg2E6aenA430mwjHi%2BhlfAuRGoc%3D&reserved=0">https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7CKevin1.Wang%40amd.com%7C96b1fda73cc94c3ec44408d85ec8f126%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637363564431270216&sdata=szoPYYfIpzZCyRrzYSR%2Fv5DbogjhMuyHMHIzWygj6Lg%3D&reserved=0</a> _______________________________________________ amd-gfx mailing list <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a> <a href="https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7CEmily.Deng%40amd.com%7C849a249868ba4128962408d85eca6667%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637363570681227058&sdata=ulesiZTX8RCcr4IQRg2E6aenA430mwjHi%2BhlfAuRGoc%3D&reserved=0">https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7CKevin1.Wang%40amd.com%7C96b1fda73cc94c3ec44408d85ec8f126%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637363564431270216&sdata=szoPYYfIpzZCyRrzYSR%2Fv5DbogjhMuyHMHIzWygj6Lg%3D&reserved=0</a><o:p></o:p> </div> </div> </div> </div> </div> </div> </div> </div> </div> </div> </body> </html>