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<p style="font-family:Arial;font-size:10pt;color:#0078D7;margin:15pt;" align="Left">
[AMD Official Use Only - Internal Distribution Only]<br>
</p>
<br>
<div>
<div class="WordSection1">
<p class="MsoNormal">Sorry for late reply…<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Yes some of the function pointers can be NULL. For those NULL function pointer, it is the call’s responsibility to *not* call them. We have been practicing like this for many function pointers before. For example, if you look at gmc_v9_0.c,
 the gmc_v9_0_ip_funcs, some function pointers are also not set. <o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I don’t think it is very necessary to add a comment, since this has been the practice without any comment before.
<a id="OWAAM77E2BB70920B49509F00A188474003F0" href="mailto:Alexander.Deucher@amd.com">
<span style="font-family:"Calibri",sans-serif;text-decoration:none">@Deucher, Alexander</span></a>
<a id="OWAAMDA1A0E9F39404726A547DCCAC0CBCC0C" href="mailto:Christian.Koenig@amd.com">
<span style="font-family:"Calibri",sans-serif;text-decoration:none">@Koenig, Christian</span></a> what do you think? Can you guys help to review this patch? Thanks<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Regards,<o:p></o:p></p>
<p class="MsoNormal">Oak<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in">
<p class="MsoNormal"><b>From:</b> Ernst Sjöstrand <ernstp@gmail.com> <br>
<b>Sent:</b> Friday, September 18, 2020 5:03 AM<br>
<b>To:</b> Zeng, Oak <Oak.Zeng@amd.com><br>
<b>Cc:</b> amd-gfx mailing list <amd-gfx@lists.freedesktop.org>; Deucher, Alexander <Alexander.Deucher@amd.com>; Koenig, Christian <Christian.Koenig@amd.com><br>
<b>Subject:</b> Re: [PATCH] drm/amdgpu: use function pointer for gfxhub functions<o:p></o:p></p>
</div>
<p class="MsoNormal"><o:p> </o:p></p>
<div>
<div>
<p class="MsoNormal"><span style="font-family:"Arial",sans-serif">Can some of them be null and others not? Perhaps write that in the comments somewhere.<o:p></o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-family:"Arial",sans-serif">Like v1 doesn't have get_fb_location for example.<o:p></o:p></span></p>
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<div>
<p class="MsoNormal"><span style="font-family:"Arial",sans-serif"><o:p> </o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-family:"Arial",sans-serif">Regards<o:p></o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-family:"Arial",sans-serif">//Ernst<o:p></o:p></span></p>
</div>
</div>
<p class="MsoNormal"><o:p> </o:p></p>
<div>
<div>
<p class="MsoNormal">Den fre 18 sep. 2020 kl 01:16 skrev Oak Zeng <<a href="mailto:Oak.Zeng@amd.com">Oak.Zeng@amd.com</a>>:<o:p></o:p></p>
</div>
<blockquote style="border:none;border-left:solid #CCCCCC 1.0pt;padding:0in 0in 0in 6.0pt;margin-left:4.8pt;margin-right:0in">
<p class="MsoNormal">gfxhub functions are now called from function pointers,<br>
instead of from asic-specific functions.<br>
<br>
Signed-off-by: Oak Zeng <<a href="mailto:Oak.Zeng@amd.com" target="_blank">Oak.Zeng@amd.com</a>><br>
---<br>
 drivers/gpu/drm/amd/amdgpu/amdgpu.h                |  4 ++<br>
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c |  3 +-<br>
 .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c   |  3 +-<br>
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c  |  5 +-<br>
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h         | 43 ++++++++++++++++++<br>
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c           | 10 ++++<br>
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h           |  1 +<br>
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c           | 13 +++++-<br>
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.h           |  2 +-<br>
 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c           | 24 +++++++---<br>
 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.h           | 10 +---<br>
 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c           | 27 +++++++----<br>
 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.h           | 12 +----<br>
 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c             | 53 +++++++++-------------<br>
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c              | 28 +++++++++---<br>
 15 files changed, 155 insertions(+), 83 deletions(-)<br>
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h<br>
index 13f92de..0d8ace9 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h<br>
@@ -104,6 +104,7 @@<br>
 #include "amdgpu_mes.h"<br>
 #include "amdgpu_umc.h"<br>
 #include "amdgpu_mmhub.h"<br>
+#include "amdgpu_gfxhub.h"<br>
 #include "amdgpu_df.h"<br>
<br>
 #define MAX_GPU_INSTANCE               16<br>
@@ -884,6 +885,9 @@ struct amdgpu_device {<br>
        /* mmhub */<br>
        struct amdgpu_mmhub             mmhub;<br>
<br>
+       /* gfxhub */<br>
+       struct amdgpu_gfxhub            gfxhub;<br>
+<br>
        /* gfx */<br>
        struct amdgpu_gfx               gfx;<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c<br>
index df0aab0..1529815 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c<br>
@@ -32,7 +32,6 @@<br>
 #include "v10_structs.h"<br>
 #include "nv.h"<br>
 #include "nvd.h"<br>
-#include "gfxhub_v2_0.h"<br>
<br>
 enum hqd_dequeue_request_type {<br>
        NO_ACTION = 0,<br>
@@ -753,7 +752,7 @@ static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,<br>
        }<br>
<br>
        /* SDMA is on gfxhub as well for Navi1* series */<br>
-       gfxhub_v2_0_setup_vm_pt_regs(adev, vmid, page_table_base);<br>
+       adev->gfxhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base);<br>
 }<br>
<br>
 const struct kfd2kgd_calls gfx_v10_kfd2kgd = {<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c<br>
index e12623a..b7ea20e 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c<br>
@@ -31,7 +31,6 @@<br>
 #include "v10_structs.h"<br>
 #include "nv.h"<br>
 #include "nvd.h"<br>
-#include "gfxhub_v2_1.h"<br>
<br>
 enum hqd_dequeue_request_type {<br>
        NO_ACTION = 0,<br>
@@ -657,7 +656,7 @@ static void set_vm_context_page_table_base_v10_3(struct kgd_dev *kgd, uint32_t v<br>
        struct amdgpu_device *adev = get_amdgpu_device(kgd);<br>
<br>
        /* SDMA is on gfxhub as well for Navi1* series */<br>
-       gfxhub_v2_1_setup_vm_pt_regs(adev, vmid, page_table_base);<br>
+       adev->gfxhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base);<br>
 }<br>
<br>
 #if 0<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c<br>
index e6aede7..b824582 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c<br>
@@ -36,9 +36,6 @@<br>
 #include "v9_structs.h"<br>
 #include "soc15.h"<br>
 #include "soc15d.h"<br>
-#include "mmhub_v1_0.h"<br>
-#include "gfxhub_v1_0.h"<br>
-<br>
<br>
 enum hqd_dequeue_request_type {<br>
        NO_ACTION = 0,<br>
@@ -703,7 +700,7 @@ void kgd_gfx_v9_set_vm_context_page_table_base(struct kgd_dev *kgd,<br>
<br>
        adev->mmhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base);<br>
<br>
-       gfxhub_v1_0_setup_vm_pt_regs(adev, vmid, page_table_base);<br>
+       adev->gfxhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base);<br>
 }<br>
<br>
 const struct kfd2kgd_calls gfx_v9_kfd2kgd = {<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h<br>
new file mode 100644<br>
index 0000000..66ebc2e<br>
--- /dev/null<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h<br>
@@ -0,0 +1,43 @@<br>
+/*<br>
+ * Copyright 2020 Advanced Micro Devices, Inc.<br>
+ *<br>
+ * Permission is hereby granted, free of charge, to any person obtaining a<br>
+ * copy of this software and associated documentation files (the "Software"),<br>
+ * to deal in the Software without restriction, including without limitation<br>
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,<br>
+ * and/or sell copies of the Software, and to permit persons to whom the<br>
+ * Software is furnished to do so, subject to the following conditions:<br>
+ *<br>
+ * The above copyright notice and this permission notice shall be included in<br>
+ * all copies or substantial portions of the Software.<br>
+ *<br>
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR<br>
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,<br>
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL<br>
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR<br>
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,<br>
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR<br>
+ * OTHER DEALINGS IN THE SOFTWARE.<br>
+ *<br>
+ */<br>
+#ifndef __AMDGPU_GFXHUB_H__<br>
+#define __AMDGPU_GFXHUB_H__<br>
+<br>
+struct amdgpu_gfxhub_funcs {<br>
+       u64 (*get_fb_location)(struct amdgpu_device *adev);<br>
+       u64 (*get_mc_fb_offset)(struct amdgpu_device *adev);<br>
+       void (*setup_vm_pt_regs)(struct amdgpu_device *adev, uint32_t vmid,<br>
+                       uint64_t page_table_base);<br>
+       int (*gart_enable)(struct amdgpu_device *adev);<br>
+<br>
+       void (*gart_disable)(struct amdgpu_device *adev);<br>
+       void (*set_fault_enable_default)(struct amdgpu_device *adev, bool value);<br>
+       void (*init)(struct amdgpu_device *adev);<br>
+       int (*get_xgmi_info)(struct amdgpu_device *adev);<br>
+};<br>
+<br>
+struct amdgpu_gfxhub {<br>
+       const struct amdgpu_gfxhub_funcs *funcs;<br>
+};<br>
+<br>
+#endif<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c<br>
index 529e463..f4187c3 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c<br>
@@ -403,3 +403,13 @@ void gfxhub_v1_0_init(struct amdgpu_device *adev)<br>
        hub->eng_addr_distance = mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -<br>
                mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;<br>
 }<br>
+<br>
+<br>
+const struct amdgpu_gfxhub_funcs gfxhub_v1_0_funcs = {<br>
+       .get_mc_fb_offset = gfxhub_v1_0_get_mc_fb_offset,<br>
+       .setup_vm_pt_regs = gfxhub_v1_0_setup_vm_pt_regs,<br>
+       .gart_enable = gfxhub_v1_0_gart_enable,<br>
+       .gart_disable = gfxhub_v1_0_gart_disable,<br>
+       .set_fault_enable_default = gfxhub_v1_0_set_fault_enable_default,<br>
+       .init = gfxhub_v1_0_init,<br>
+};<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h<br>
index 92d3a70..0c46672 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h<br>
@@ -33,4 +33,5 @@ u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev);<br>
 void gfxhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,<br>
                                uint64_t page_table_base);<br>
<br>
+extern const struct amdgpu_gfxhub_funcs gfxhub_v1_0_funcs;<br>
 #endif<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c<br>
index c0ab71d..1e24b6d 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c<br>
@@ -21,6 +21,7 @@<br>
  *<br>
  */<br>
 #include "amdgpu.h"<br>
+#include "gfxhub_v1_0.h"<br>
 #include "gfxhub_v1_1.h"<br>
<br>
 #include "gc/gc_9_2_1_offset.h"<br>
@@ -28,7 +29,7 @@<br>
<br>
 #include "soc15_common.h"<br>
<br>
-int gfxhub_v1_1_get_xgmi_info(struct amdgpu_device *adev)<br>
+static int gfxhub_v1_1_get_xgmi_info(struct amdgpu_device *adev)<br>
 {<br>
        u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL);<br>
        u32 max_region =<br>
@@ -66,3 +67,13 @@ int gfxhub_v1_1_get_xgmi_info(struct amdgpu_device *adev)<br>
<br>
        return 0;<br>
 }<br>
+<br>
+const struct amdgpu_gfxhub_funcs gfxhub_v1_1_funcs = {<br>
+       .get_mc_fb_offset = gfxhub_v1_0_get_mc_fb_offset,<br>
+       .setup_vm_pt_regs = gfxhub_v1_0_setup_vm_pt_regs,<br>
+       .gart_enable = gfxhub_v1_0_gart_enable,<br>
+       .gart_disable = gfxhub_v1_0_gart_disable,<br>
+       .set_fault_enable_default = gfxhub_v1_0_set_fault_enable_default,<br>
+       .init = gfxhub_v1_0_init,<br>
+       .get_xgmi_info = gfxhub_v1_1_get_xgmi_info,<br>
+};<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.h b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.h<br>
index d753cf2..ae5759f 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.h<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.h<br>
@@ -24,6 +24,6 @@<br>
 #ifndef __GFXHUB_V1_1_H__<br>
 #define __GFXHUB_V1_1_H__<br>
<br>
-int gfxhub_v1_1_get_xgmi_info(struct amdgpu_device *adev);<br>
+extern const struct amdgpu_gfxhub_funcs gfxhub_v1_1_funcs;<br>
<br>
 #endif<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c<br>
index b882ac5..3386cfa 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c<br>
@@ -102,7 +102,7 @@ gfxhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev,<br>
                GCVM_L2_PROTECTION_FAULT_STATUS, RW));<br>
 }<br>
<br>
-u64 gfxhub_v2_0_get_fb_location(struct amdgpu_device *adev)<br>
+static u64 gfxhub_v2_0_get_fb_location(struct amdgpu_device *adev)<br>
 {<br>
        u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE);<br>
<br>
@@ -112,12 +112,12 @@ u64 gfxhub_v2_0_get_fb_location(struct amdgpu_device *adev)<br>
        return base;<br>
 }<br>
<br>
-u64 gfxhub_v2_0_get_mc_fb_offset(struct amdgpu_device *adev)<br>
+static u64 gfxhub_v2_0_get_mc_fb_offset(struct amdgpu_device *adev)<br>
 {<br>
        return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24;<br>
 }<br>
<br>
-void gfxhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,<br>
+static void gfxhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,<br>
                                uint64_t page_table_base)<br>
 {<br>
        struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];<br>
@@ -347,7 +347,7 @@ static void gfxhub_v2_0_program_invalidation(struct amdgpu_device *adev)<br>
        }<br>
 }<br>
<br>
-int gfxhub_v2_0_gart_enable(struct amdgpu_device *adev)<br>
+static int gfxhub_v2_0_gart_enable(struct amdgpu_device *adev)<br>
 {<br>
        /* GART Enable. */<br>
        gfxhub_v2_0_init_gart_aperture_regs(adev);<br>
@@ -363,7 +363,7 @@ int gfxhub_v2_0_gart_enable(struct amdgpu_device *adev)<br>
        return 0;<br>
 }<br>
<br>
-void gfxhub_v2_0_gart_disable(struct amdgpu_device *adev)<br>
+static void gfxhub_v2_0_gart_disable(struct amdgpu_device *adev)<br>
 {<br>
        struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];<br>
        u32 tmp;<br>
@@ -394,7 +394,7 @@ void gfxhub_v2_0_gart_disable(struct amdgpu_device *adev)<br>
  * @adev: amdgpu_device pointer<br>
  * @value: true redirects VM faults to the default page<br>
  */<br>
-void gfxhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev,<br>
+static void gfxhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev,<br>
                                          bool value)<br>
 {<br>
        u32 tmp;<br>
@@ -436,7 +436,7 @@ static const struct amdgpu_vmhub_funcs gfxhub_v2_0_vmhub_funcs = {<br>
        .get_invalidate_req = gfxhub_v2_0_get_invalidate_req,<br>
 };<br>
<br>
-void gfxhub_v2_0_init(struct amdgpu_device *adev)<br>
+static void gfxhub_v2_0_init(struct amdgpu_device *adev)<br>
 {<br>
        struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];<br>
<br>
@@ -477,3 +477,13 @@ void gfxhub_v2_0_init(struct amdgpu_device *adev)<br>
<br>
        hub->vmhub_funcs = &gfxhub_v2_0_vmhub_funcs;<br>
 }<br>
+<br>
+const struct amdgpu_gfxhub_funcs gfxhub_v2_0_funcs = {<br>
+       .get_fb_location = gfxhub_v2_0_get_fb_location,<br>
+       .get_mc_fb_offset = gfxhub_v2_0_get_mc_fb_offset,<br>
+       .setup_vm_pt_regs = gfxhub_v2_0_setup_vm_pt_regs,<br>
+       .gart_enable = gfxhub_v2_0_gart_enable,<br>
+       .gart_disable = gfxhub_v2_0_gart_disable,<br>
+       .set_fault_enable_default = gfxhub_v2_0_set_fault_enable_default,<br>
+       .init = gfxhub_v2_0_init,<br>
+};<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.h b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.h<br>
index 392b8cd..9ddc35cd 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.h<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.h<br>
@@ -24,14 +24,6 @@<br>
 #ifndef __GFXHUB_V2_0_H__<br>
 #define __GFXHUB_V2_0_H__<br>
<br>
-u64 gfxhub_v2_0_get_fb_location(struct amdgpu_device *adev);<br>
-int gfxhub_v2_0_gart_enable(struct amdgpu_device *adev);<br>
-void gfxhub_v2_0_gart_disable(struct amdgpu_device *adev);<br>
-void gfxhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev,<br>
-                                         bool value);<br>
-void gfxhub_v2_0_init(struct amdgpu_device *adev);<br>
-u64 gfxhub_v2_0_get_mc_fb_offset(struct amdgpu_device *adev);<br>
-void gfxhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,<br>
-                               uint64_t page_table_base);<br>
+extern const struct amdgpu_gfxhub_funcs gfxhub_v2_0_funcs;<br>
<br>
 #endif<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c<br>
index 237a9ff..98f2c53 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c<br>
@@ -102,7 +102,7 @@ gfxhub_v2_1_print_l2_protection_fault_status(struct amdgpu_device *adev,<br>
                GCVM_L2_PROTECTION_FAULT_STATUS, RW));<br>
 }<br>
<br>
-u64 gfxhub_v2_1_get_fb_location(struct amdgpu_device *adev)<br>
+static u64 gfxhub_v2_1_get_fb_location(struct amdgpu_device *adev)<br>
 {<br>
        u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE);<br>
<br>
@@ -112,12 +112,12 @@ u64 gfxhub_v2_1_get_fb_location(struct amdgpu_device *adev)<br>
        return base;<br>
 }<br>
<br>
-u64 gfxhub_v2_1_get_mc_fb_offset(struct amdgpu_device *adev)<br>
+static u64 gfxhub_v2_1_get_mc_fb_offset(struct amdgpu_device *adev)<br>
 {<br>
        return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24;<br>
 }<br>
<br>
-void gfxhub_v2_1_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,<br>
+static void gfxhub_v2_1_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,<br>
                                uint64_t page_table_base)<br>
 {<br>
        struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];<br>
@@ -348,7 +348,7 @@ static void gfxhub_v2_1_program_invalidation(struct amdgpu_device *adev)<br>
        }<br>
 }<br>
<br>
-int gfxhub_v2_1_gart_enable(struct amdgpu_device *adev)<br>
+static int gfxhub_v2_1_gart_enable(struct amdgpu_device *adev)<br>
 {<br>
        if (amdgpu_sriov_vf(adev)) {<br>
                /*<br>
@@ -376,7 +376,7 @@ int gfxhub_v2_1_gart_enable(struct amdgpu_device *adev)<br>
        return 0;<br>
 }<br>
<br>
-void gfxhub_v2_1_gart_disable(struct amdgpu_device *adev)<br>
+static void gfxhub_v2_1_gart_disable(struct amdgpu_device *adev)<br>
 {<br>
        struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];<br>
        u32 tmp;<br>
@@ -405,7 +405,7 @@ void gfxhub_v2_1_gart_disable(struct amdgpu_device *adev)<br>
  * @adev: amdgpu_device pointer<br>
  * @value: true redirects VM faults to the default page<br>
  */<br>
-void gfxhub_v2_1_set_fault_enable_default(struct amdgpu_device *adev,<br>
+static void gfxhub_v2_1_set_fault_enable_default(struct amdgpu_device *adev,<br>
                                          bool value)<br>
 {<br>
        u32 tmp;<br>
@@ -454,7 +454,7 @@ static const struct amdgpu_vmhub_funcs gfxhub_v2_1_vmhub_funcs = {<br>
        .get_invalidate_req = gfxhub_v2_1_get_invalidate_req,<br>
 };<br>
<br>
-void gfxhub_v2_1_init(struct amdgpu_device *adev)<br>
+static void gfxhub_v2_1_init(struct amdgpu_device *adev)<br>
 {<br>
        struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];<br>
<br>
@@ -496,7 +496,7 @@ void gfxhub_v2_1_init(struct amdgpu_device *adev)<br>
        hub->vmhub_funcs = &gfxhub_v2_1_vmhub_funcs;<br>
 }<br>
<br>
-int gfxhub_v2_1_get_xgmi_info(struct amdgpu_device *adev)<br>
+static int gfxhub_v2_1_get_xgmi_info(struct amdgpu_device *adev)<br>
 {<br>
        u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_CNTL);<br>
        u32 max_region =<br>
@@ -531,3 +531,14 @@ int gfxhub_v2_1_get_xgmi_info(struct amdgpu_device *adev)<br>
<br>
        return 0;<br>
 }<br>
+<br>
+const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = {<br>
+       .get_fb_location = gfxhub_v2_1_get_fb_location,<br>
+       .get_mc_fb_offset = gfxhub_v2_1_get_mc_fb_offset,<br>
+       .setup_vm_pt_regs = gfxhub_v2_1_setup_vm_pt_regs,<br>
+       .gart_enable = gfxhub_v2_1_gart_enable,<br>
+       .gart_disable = gfxhub_v2_1_gart_disable,<br>
+       .set_fault_enable_default = gfxhub_v2_1_set_fault_enable_default,<br>
+       .init = gfxhub_v2_1_init,<br>
+       .get_xgmi_info = gfxhub_v2_1_get_xgmi_info,<br>
+};<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.h b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.h<br>
index 3452a4e..f75c2ec 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.h<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.h<br>
@@ -24,16 +24,6 @@<br>
 #ifndef __GFXHUB_V2_1_H__<br>
 #define __GFXHUB_V2_1_H__<br>
<br>
-u64 gfxhub_v2_1_get_fb_location(struct amdgpu_device *adev);<br>
-int gfxhub_v2_1_gart_enable(struct amdgpu_device *adev);<br>
-void gfxhub_v2_1_gart_disable(struct amdgpu_device *adev);<br>
-void gfxhub_v2_1_set_fault_enable_default(struct amdgpu_device *adev,<br>
-                                         bool value);<br>
-void gfxhub_v2_1_init(struct amdgpu_device *adev);<br>
-u64 gfxhub_v2_1_get_mc_fb_offset(struct amdgpu_device *adev);<br>
-void gfxhub_v2_1_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,<br>
-                               uint64_t page_table_base);<br>
-<br>
-int gfxhub_v2_1_get_xgmi_info(struct amdgpu_device *adev);<br>
+extern const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs;<br>
<br>
 #endif<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c<br>
index 31359e5..dbc8b76 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c<br>
@@ -634,11 +634,26 @@ static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev)<br>
        adev->mmhub.funcs = &mmhub_v2_0_funcs;<br>
 }<br>
<br>
+static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev)<br>
+{<br>
+       switch (adev->asic_type) {<br>
+       case CHIP_SIENNA_CICHLID:<br>
+       case CHIP_NAVY_FLOUNDER:<br>
+               adev->gfxhub.funcs = &gfxhub_v2_1_funcs;<br>
+               break;<br>
+       default:<br>
+               adev->gfxhub.funcs = &gfxhub_v2_0_funcs;<br>
+               break;<br>
+       }<br>
+}<br>
+<br>
+<br>
 static int gmc_v10_0_early_init(void *handle)<br>
 {<br>
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;<br>
<br>
        gmc_v10_0_set_mmhub_funcs(adev);<br>
+       gmc_v10_0_set_gfxhub_funcs(adev);<br>
        gmc_v10_0_set_gmc_funcs(adev);<br>
        gmc_v10_0_set_irq_funcs(adev);<br>
        gmc_v10_0_set_umc_funcs(adev);<br>
@@ -676,11 +691,7 @@ static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev,<br>
 {<br>
        u64 base = 0;<br>
<br>
-       if (adev->asic_type == CHIP_SIENNA_CICHLID ||<br>
-           adev->asic_type == CHIP_NAVY_FLOUNDER)<br>
-               base = gfxhub_v2_1_get_fb_location(adev);<br>
-       else<br>
-               base = gfxhub_v2_0_get_fb_location(adev);<br>
+       base = adev->gfxhub.funcs->get_fb_location(adev);<br>
<br>
        /* add the xgmi offset of the physical node */<br>
        base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;<br>
@@ -689,11 +700,7 @@ static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev,<br>
        amdgpu_gmc_gart_location(adev, mc);<br>
<br>
        /* base offset of vram pages */<br>
-       if (adev->asic_type == CHIP_SIENNA_CICHLID ||<br>
-           adev->asic_type == CHIP_NAVY_FLOUNDER)<br>
-               adev->vm_manager.vram_base_offset = gfxhub_v2_1_get_mc_fb_offset(adev);<br>
-       else<br>
-               adev->vm_manager.vram_base_offset = gfxhub_v2_0_get_mc_fb_offset(adev);<br>
+       adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev);<br>
<br>
        /* add the xgmi offset of the physical node */<br>
        adev->vm_manager.vram_base_offset +=<br>
@@ -777,11 +784,7 @@ static int gmc_v10_0_sw_init(void *handle)<br>
        int r, vram_width = 0, vram_type = 0, vram_vendor = 0;<br>
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;<br>
<br>
-       if (adev->asic_type == CHIP_SIENNA_CICHLID ||<br>
-           adev->asic_type == CHIP_NAVY_FLOUNDER)<br>
-               gfxhub_v2_1_init(adev);<br>
-       else<br>
-               gfxhub_v2_0_init(adev);<br>
+       adev->gfxhub.funcs->init(adev);<br>
<br>
        adev->mmhub.funcs->init(adev);<br>
<br>
@@ -852,7 +855,7 @@ static int gmc_v10_0_sw_init(void *handle)<br>
        }<br>
<br>
        if (adev->gmc.xgmi.supported) {<br>
-               r = gfxhub_v2_1_get_xgmi_info(adev);<br>
+               r = adev->gfxhub.funcs->get_xgmi_info(adev);<br>
                if (r)<br>
                        return r;<br>
        }<br>
@@ -944,11 +947,7 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)<br>
        if (r)<br>
                return r;<br>
<br>
-       if (adev->asic_type == CHIP_SIENNA_CICHLID ||<br>
-           adev->asic_type == CHIP_NAVY_FLOUNDER)<br>
-               r = gfxhub_v2_1_gart_enable(adev);<br>
-       else<br>
-               r = gfxhub_v2_0_gart_enable(adev);<br>
+       r = adev->gfxhub.funcs->gart_enable(adev);<br>
        if (r)<br>
                return r;<br>
<br>
@@ -969,11 +968,7 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)<br>
        value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?<br>
                false : true;<br>
<br>
-       if (adev->asic_type == CHIP_SIENNA_CICHLID ||<br>
-           adev->asic_type == CHIP_NAVY_FLOUNDER)<br>
-               gfxhub_v2_1_set_fault_enable_default(adev, value);<br>
-       else<br>
-               gfxhub_v2_0_set_fault_enable_default(adev, value);<br>
+       adev->gfxhub.funcs->set_fault_enable_default(adev, value);<br>
        adev->mmhub.funcs->set_fault_enable_default(adev, value);<br>
        gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0);<br>
        gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0);<br>
@@ -1014,11 +1009,7 @@ static int gmc_v10_0_hw_init(void *handle)<br>
  */<br>
 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev)<br>
 {<br>
-       if (adev->asic_type == CHIP_SIENNA_CICHLID ||<br>
-           adev->asic_type == CHIP_NAVY_FLOUNDER)<br>
-               gfxhub_v2_1_gart_disable(adev);<br>
-       else<br>
-               gfxhub_v2_0_gart_disable(adev);<br>
+       adev->gfxhub.funcs->gart_disable(adev);<br>
        adev->mmhub.funcs->gart_disable(adev);<br>
        amdgpu_gart_table_vram_unpin(adev);<br>
 }<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c<br>
index d5679d1..7e481af 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c<br>
@@ -1164,6 +1164,19 @@ static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev)<br>
        }<br>
 }<br>
<br>
+static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev)<br>
+{<br>
+       switch (adev->asic_type) {<br>
+       case CHIP_ARCTURUS:<br>
+       case CHIP_VEGA20:<br>
+               adev->gfxhub.funcs = &gfxhub_v1_1_funcs;<br>
+               break;<br>
+       default:<br>
+               adev->gfxhub.funcs = &gfxhub_v1_0_funcs;<br>
+               break;<br>
+       }<br>
+}<br>
+<br>
 static int gmc_v9_0_early_init(void *handle)<br>
 {<br>
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;<br>
@@ -1172,6 +1185,7 @@ static int gmc_v9_0_early_init(void *handle)<br>
        gmc_v9_0_set_irq_funcs(adev);<br>
        gmc_v9_0_set_umc_funcs(adev);<br>
        gmc_v9_0_set_mmhub_funcs(adev);<br>
+       gmc_v9_0_set_gfxhub_funcs(adev);<br>
<br>
        adev->gmc.shared_aperture_start = 0x2000000000000000ULL;<br>
        adev->gmc.shared_aperture_end =<br>
@@ -1234,7 +1248,7 @@ static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,<br>
        amdgpu_gmc_gart_location(adev, mc);<br>
        amdgpu_gmc_agp_location(adev, mc);<br>
        /* base offset of vram pages */<br>
-       adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);<br>
+       adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev);<br>
<br>
        /* XXX: add the xgmi offset of the physical node? */<br>
        adev->vm_manager.vram_base_offset +=<br>
@@ -1269,7 +1283,7 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)<br>
<br>
 #ifdef CONFIG_X86_64<br>
        if (adev->flags & AMD_IS_APU) {<br>
-               adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev);<br>
+               adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev);<br>
                adev->gmc.aper_size = adev->gmc.real_vram_size;<br>
        }<br>
 #endif<br>
@@ -1339,7 +1353,7 @@ static int gmc_v9_0_sw_init(void *handle)<br>
        int r, vram_width = 0, vram_type = 0, vram_vendor = 0;<br>
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;<br>
<br>
-       gfxhub_v1_0_init(adev);<br>
+       adev->gfxhub.funcs->init(adev);<br>
<br>
        adev->mmhub.funcs->init(adev);<br>
<br>
@@ -1453,7 +1467,7 @@ static int gmc_v9_0_sw_init(void *handle)<br>
        adev->need_swiotlb = drm_need_swiotlb(44);<br>
<br>
        if (adev->gmc.xgmi.supported) {<br>
-               r = gfxhub_v1_1_get_xgmi_info(adev);<br>
+               r = adev->gfxhub.funcs->get_xgmi_info(adev);<br>
                if (r)<br>
                        return r;<br>
        }<br>
@@ -1569,7 +1583,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)<br>
        if (r)<br>
                return r;<br>
<br>
-       r = gfxhub_v1_0_gart_enable(adev);<br>
+       r = adev->gfxhub.funcs->gart_enable(adev);<br>
        if (r)<br>
                return r;<br>
<br>
@@ -1636,7 +1650,7 @@ static int gmc_v9_0_hw_init(void *handle)<br>
                value = true;<br>
<br>
        if (!amdgpu_sriov_vf(adev)) {<br>
-               gfxhub_v1_0_set_fault_enable_default(adev, value);<br>
+               adev->gfxhub.funcs->set_fault_enable_default(adev, value);<br>
                adev->mmhub.funcs->set_fault_enable_default(adev, value);<br>
        }<br>
        for (i = 0; i < adev->num_vmhubs; ++i)<br>
@@ -1659,7 +1673,7 @@ static int gmc_v9_0_hw_init(void *handle)<br>
  */<br>
 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)<br>
 {<br>
-       gfxhub_v1_0_gart_disable(adev);<br>
+       adev->gfxhub.funcs->gart_disable(adev);<br>
        adev->mmhub.funcs->gart_disable(adev);<br>
        amdgpu_gart_table_vram_unpin(adev);<br>
 }<br>
-- <br>
2.7.4<br>
<br>
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