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[AMD Official Use Only - Internal Distribution Only]<br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" color="#000000" style="font-size:11pt"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Likun Gao <likun.gao@amd.com><br>
<b>Sent:</b> Thursday, October 15, 2020 12:03 PM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Gao, Likun <Likun.Gao@amd.com><br>
<b>Subject:</b> [PATCH] drm/amdgpu: add function to program pbb mode for sienna cichlid</font>
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<div class="BodyFragment"><font size="2"><span style="font-size:11pt">
<div class="PlainText">From: Likun Gao <Likun.Gao@amd.com><br>
<br>
Add function for sienna_cichlid to force PBB workload mode to zero by<br>
checking whether there have SE been harvested.<br>
<br>
Signed-off-by: Likun Gao <Likun.Gao@amd.com><br>
Change-Id: I3bf2fe0b976affe26c829ac67bee176018f13fe9<br>
---<br>
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 62 ++++++++++++++++++++++++++<br>
1 file changed, 62 insertions(+)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c<br>
index 65804137b7f8..aa48eab85c7a 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c<br>
@@ -112,6 +112,22 @@<br>
#define mmCP_HYP_ME_UCODE_DATA 0x5817<br>
#define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1<br>
<br>
+//CC_GC_SA_UNIT_DISABLE<br>
+#define mmCC_GC_SA_UNIT_DISABLE 0x0fe9<br>
+#define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0<br>
+#define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8<br>
+#define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L<br>
+//GC_USER_SA_UNIT_DISABLE<br>
+#define mmGC_USER_SA_UNIT_DISABLE 0x0fea<br>
+#define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0<br>
+#define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8<br>
+#define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L<br>
+//PA_SC_ENHANCE_3<br>
+#define mmPA_SC_ENHANCE_3 0x1085<br>
+#define mmPA_SC_ENHANCE_3_BASE_IDX 0<br>
+#define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3<br>
+#define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L<br>
+<br>
MODULE_FIRMWARE("amdgpu/navi10_ce.bin");<br>
MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");<br>
MODULE_FIRMWARE("amdgpu/navi10_me.bin");<br>
@@ -3188,6 +3204,8 @@ static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);<br>
static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);<br>
static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);<br>
static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);<br>
+static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);<br>
+static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);<br>
<br>
static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)<br>
{<br>
@@ -6990,6 +7008,9 @@ static int gfx_v10_0_hw_init(void *handle)<br>
if (r)<br>
return r;<br>
<br>
+ if (adev->asic_type == CHIP_SIENNA_CICHLID)<br>
+ gfx_v10_3_program_pbb_mode(adev);<br>
+<br>
return r;<br>
}<br>
<br>
@@ -8841,6 +8862,47 @@ static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,<br>
return 0;<br>
}<br>
<br>
+static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)<br>
+{<br>
+ uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;<br>
+<br>
+ efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);<br>
+ efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;<br>
+ efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;<br>
+<br>
+ vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);<br>
+ vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;<br>
+ vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;</div>
<div class="PlainText"><br>
</div>
<div class="PlainText">[kevin]:</div>
<div class="PlainText">the above codes can be replaced with helper macro of "REG_GET_FIELD".</div>
<div class="PlainText">#define REG_GET_FIELD(value, reg, field) \</div>
<div class="PlainText"> (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))<br>
</div>
<div class="PlainText">+<br>
+ max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *<br>
+ adev->gfx.config.max_shader_engines);<br>
+ disabled_sa = efuse_setting | vbios_setting;<br>
+ disabled_sa &= max_sa_mask;<br>
+<br>
+ return disabled_sa;<br>
+}<br>
+<br>
+static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)<br>
+{<br>
+ uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;<br>
+ uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;<br>
+<br>
+ disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);<br>
+<br>
+ max_sa_per_se = adev->gfx.config.max_sh_per_se;<br>
+ max_sa_per_se_mask = (1 << max_sa_per_se) - 1;<br>
+ max_shader_engines = adev->gfx.config.max_shader_engines;<br>
+<br>
+ for (se_index = 0; max_shader_engines > se_index; se_index++) {<br>
+ disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);<br>
+ disabled_sa_per_se &= max_sa_per_se_mask;<br>
+ if (disabled_sa_per_se == max_sa_per_se_mask) {<br>
+ WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);<br>
+ break;<br>
+ }<br>
+ }<br>
+}<br>
+<br>
const struct amdgpu_ip_block_version gfx_v10_0_ip_block =<br>
{<br>
.type = AMD_IP_BLOCK_TYPE_GFX,<br>
-- <br>
2.25.1<br>
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