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[AMD Official Use Only - Internal Distribution Only]<br>
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Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com><br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Aurabindo Pillai <aurabindo.pillai@amd.com><br>
<b>Sent:</b> October 23, 2020 1:09 PM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>; Galiffi, David <David.Galiffi@amd.com><br>
<b>Subject:</b> [PATCH] drm/amd/display: Fixed panic during seamless boot.</font>
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<div class="PlainText">From: David Galiffi <David.Galiffi@amd.com><br>
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[why]<br>
get_pixel_clk_frequency_100hz is undefined in clock_source_funcs.<br>
<br>
[how]<br>
set function pointer: ".get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz"<br>
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Signed-off-by: David Galiffi <David.Galiffi@amd.com><br>
---<br>
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 3 ++-<br>
1 file changed, 2 insertions(+), 1 deletion(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c<br>
index 512b26b3e3fd..589c7fb71480 100644<br>
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c<br>
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c<br>
@@ -1149,7 +1149,8 @@ static uint32_t dcn3_get_pix_clk_dividers(<br>
static const struct clock_source_funcs dcn3_clk_src_funcs = {<br>
.cs_power_down = dce110_clock_source_power_down,<br>
.program_pix_clk = dcn3_program_pix_clk,<br>
- .get_pix_clk_dividers = dcn3_get_pix_clk_dividers<br>
+ .get_pix_clk_dividers = dcn3_get_pix_clk_dividers,<br>
+ .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz<br>
};<br>
#endif<br>
/*****************************************/<br>
-- <br>
2.25.1<br>
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