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[AMD Official Use Only - Internal Distribution Only]<br>
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Looks sane to me.</div>
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Acked-by: Slava Abramov <slava.abramov@amd.com></div>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Alex Deucher <alexdeucher@gmail.com><br>
<b>Sent:</b> Tuesday, October 27, 2020 11:20 AM<br>
<b>To:</b> amd-gfx list <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Deucher, Alexander <Alexander.Deucher@amd.com><br>
<b>Subject:</b> Re: [PATCH] drm/amdgpu/display: re-add surface size calculation in dcn30_hwseq.c</font>
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<div class="PlainText">Ping?<br>
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On Mon, Oct 26, 2020 at 12:14 PM Alex Deucher <alexdeucher@gmail.com> wrote:<br>
><br>
> This is required for MALL. Was accidently removed in PRS update.<br>
><br>
> Fixes: 48e48e598478 ("drm/amd/display: Disable idle optimization when PSR is enabled")<br>
> Fixes: 52f2e83e2fe5 ("drm/amdgpu/display: add MALL support (v2)")<br>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com><br>
> ---<br>
> .../gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 15 +++++++++++++++<br>
> 1 file changed, 15 insertions(+)<br>
><br>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c<br>
> index f3ae208850b0..cc2eca8c9a62 100644<br>
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c<br>
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c<br>
> @@ -715,6 +715,21 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)<br>
> break;<br>
> }<br>
><br>
> + if (dc->current_state->stream_count == 1 // single display only<br>
> + && dc->current_state->stream_status[0].plane_count == 1 // single surface only<br>
> + && dc->current_state->stream_status[0].plane_states[0]->address.page_table_base.quad_part == 0 // no VM<br>
> + // Only 8 and 16 bit formats<br>
> + && dc->current_state->stream_status[0].plane_states[0]->format <= SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F<br>
> + && dc->current_state->stream_status[0].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888) {<br>
> + surface_size = dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_pitch *<br>
> + dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_size.height *<br>
> + (dc->current_state->stream_status[0].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ?<br>
> + 8 : 4);<br>
> + } else {<br>
> + // TODO: remove hard code size<br>
> + surface_size = 128 * 1024 * 1024;<br>
> + }<br>
> +<br>
> // TODO: remove hard code size<br>
> if (surface_size < 128 * 1024 * 1024) {<br>
> refresh_hz = div_u64((unsigned long long) dc->current_state->streams[0]->timing.pix_clk_100hz *<br>
> --<br>
> 2.25.4<br>
><br>
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