<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns:m="http://schemas.microsoft.com/office/2004/12/omml" xmlns="http://www.w3.org/TR/REC-html40"> <head> <meta http-equiv="Content-Type" content="text/html; charset=utf-8"> <meta name="Generator" content="Microsoft Word 15 (filtered medium)"> <style></style> </head> <body lang="EN-US" link="blue" vlink="purple" style="word-wrap:break-word"> <div class="WordSection1"> <p class="msipheader251902e5" style="margin:0in"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:#317100">[AMD Public Use]</span><o:p></o:p></p> <p class="MsoNormal"><o:p> </o:p></p> <p class="MsoNormal">Thanks Alex, Christian, <o:p></o:p></p> <p class="MsoNormal">Let me quickly run this patch through someone in DAL team, and see how it looks. <o:p></o:p></p> <p class="MsoNormal"><o:p> </o:p></p> <p class="MsoNormal">Regards<o:p></o:p></p> <p class="MsoNormal">Shashank<o:p></o:p></p> <p class="MsoNormal"><o:p> </o:p></p> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in"> <p class="MsoNormal"><b>From:</b> Deucher, Alexander <Alexander.Deucher@amd.com> <br> <b>Sent:</b> Wednesday, November 4, 2020 8:03 PM<br> <b>To:</b> Koenig, Christian <Christian.Koenig@amd.com>; Sharma, Shashank <Shashank.Sharma@amd.com>; amd-gfx@lists.freedesktop.org<br> <b>Cc:</b> Qin, Eddy <Eddy.Qin@amd.com><br> <b>Subject:</b> Re: [PATCH] drm/amdgpu: clip the ref divider max value at 100<o:p></o:p></p> </div> </div> <p class="MsoNormal"><o:p> </o:p></p> <div> <p class="MsoNormal"><span style="font-size:12.0pt;color:black">yeah, ideally. Just need to get support for analog encoders.<o:p></o:p></span></p> </div> <div> <p class="MsoNormal"><span style="font-size:12.0pt;color:black"><o:p> </o:p></span></p> </div> <div> <p class="MsoNormal"><span style="font-size:12.0pt;color:black">Alex<o:p></o:p></span></p> </div> <div> <p class="MsoNormal"><span style="font-size:12.0pt;color:black"><o:p> </o:p></span></p> </div> <div class="MsoNormal" align="center" style="text-align:center"> <hr size="1" width="98%" align="center"> </div> <div id="divRplyFwdMsg"> <p class="MsoNormal"><b><span style="color:black">From:</span></b><span style="color:black"> Koenig, Christian <<a href="mailto:Christian.Koenig@amd.com">Christian.Koenig@amd.com</a>><br> <b>Sent:</b> Wednesday, November 4, 2020 9:31 AM<br> <b>To:</b> Deucher, Alexander <<a href="mailto:Alexander.Deucher@amd.com">Alexander.Deucher@amd.com</a>>; Sharma, Shashank <<a href="mailto:Shashank.Sharma@amd.com">Shashank.Sharma@amd.com</a>>; <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a> <<a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a>><br> <b>Cc:</b> Qin, Eddy <<a href="mailto:Eddy.Qin@amd.com">Eddy.Qin@amd.com</a>><br> <b>Subject:</b> Re: [PATCH] drm/amdgpu: clip the ref divider max value at 100</span> <o:p></o:p></p> <div> <p class="MsoNormal"> <o:p></o:p></p> </div> </div> <div> <div> <p class="MsoNormal">In the long term we probably want to nuke this code anyway and switch to the DC code, don't we?<br> <br> Christian.<br> <br> Am 04.11.20 um 15:23 schrieb Deucher, Alexander:<o:p></o:p></p> </div> <blockquote style="margin-top:5.0pt;margin-bottom:5.0pt"> <div> <p class="MsoNormal"><span style="font-size:12.0pt;color:black">You might want to talk to the DAL team, they may have some advice. In general, I would say test it as well as you can. It's probably safe as radeon is still the default driver for SI parts and generally seems to be working well there.<o:p></o:p></span></p> </div> <div> <p class="MsoNormal"><span style="font-size:12.0pt;color:black"><o:p> </o:p></span></p> </div> <div> <p class="MsoNormal"><span style="font-size:12.0pt;color:black">Alex<o:p></o:p></span></p> </div> <div> <p class="MsoNormal"><span style="font-size:12.0pt;color:black"><o:p> </o:p></span></p> </div> <div class="MsoNormal" align="center" style="text-align:center"> <hr size="1" width="98%" align="center"> </div> <div id="x_divRplyFwdMsg"> <p class="MsoNormal"><b><span style="color:black">From:</span></b><span style="color:black"> Sharma, Shashank <a href="mailto:Shashank.Sharma@amd.com"><Shashank.Sharma@amd.com></a><br> <b>Sent:</b> Wednesday, November 4, 2020 9:11 AM<br> <b>To:</b> Deucher, Alexander <a href="mailto:Alexander.Deucher@amd.com"><Alexander.Deucher@amd.com></a>; Koenig, Christian <a href="mailto:Christian.Koenig@amd.com"><Christian.Koenig@amd.com></a>; <a href="mailto:amd-gfx@lists.freedesktop.org"> amd-gfx@lists.freedesktop.org</a> <a href="mailto:amd-gfx@lists.freedesktop.org"> <amd-gfx@lists.freedesktop.org></a><br> <b>Cc:</b> Qin, Eddy <a href="mailto:Eddy.Qin@amd.com"><Eddy.Qin@amd.com></a><br> <b>Subject:</b> Re: [PATCH] drm/amdgpu: clip the ref divider max value at 100</span> <o:p></o:p></p> <div> <p class="MsoNormal"> <o:p></o:p></p> </div> </div> <div> <p>Thanks Alex, Same question here, <o:p></o:p></p> <p>Should we go through some extensive test routine due to change in PLL values, or is it OK to go ahead based on our experience from Radeon values ? <o:p></o:p></p> <p><o:p> </o:p></p> <p>Regards<o:p></o:p></p> <p>Shashank<o:p></o:p></p> <p><o:p> </o:p></p> <div> <p class="MsoNormal">On 04/11/20 7:36 pm, Deucher, Alexander wrote:<o:p></o:p></p> </div> <blockquote style="margin-top:5.0pt;margin-bottom:5.0pt"> <div> <p class="MsoNormal"><span style="font-size:12.0pt;color:black">Acked-by: Alex Deucher <a href="mailto:alexander.deucher@amd.com"><alexander.deucher@amd.com></a><o:p></o:p></span></p> </div> <div class="MsoNormal" align="center" style="text-align:center"> <hr size="1" width="98%" align="center"> </div> <div id="x_x_divRplyFwdMsg"> <p class="MsoNormal"><b><span style="color:black">From:</span></b><span style="color:black"> Koenig, Christian <a href="mailto:Christian.Koenig@amd.com"><Christian.Koenig@amd.com></a><br> <b>Sent:</b> Wednesday, November 4, 2020 6:54 AM<br> <b>To:</b> Sharma, Shashank <a href="mailto:Shashank.Sharma@amd.com"><Shashank.Sharma@amd.com></a>; <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a> <a href="mailto:amd-gfx@lists.freedesktop.org"> <amd-gfx@lists.freedesktop.org></a><br> <b>Cc:</b> Deucher, Alexander <a href="mailto:Alexander.Deucher@amd.com"><Alexander.Deucher@amd.com></a>; Qin, Eddy <a href="mailto:Eddy.Qin@amd.com"><Eddy.Qin@amd.com></a><br> <b>Subject:</b> Re: [PATCH] drm/amdgpu: clip the ref divider max value at 100</span> <o:p></o:p></p> <div> <p class="MsoNormal"> <o:p></o:p></p> </div> </div> <div> <div> <p class="MsoNormal" style="margin-bottom:12.0pt">Am 04.11.20 um 11:40 schrieb Sharma, Shashank:<br> > [AMD Public Use]<br> ><br> > Hello Christian,<br> > Yes, that 100 is hardcoded in Radeon, and git blame says it was one of your patches which made it 100 from 128 <span style="font-family:"Segoe UI Emoji",sans-serif">😊</span>.<br> > Would you mind having a look at commit id: 4b21ce1b4b5d262e7d4656b8ececc891fc3cb806 ?<br> <br> Ah, yes that one :)<br> <br> Yeah the background is that this was just an educated guess because I <br> couldn't find anybody which could tell me what the real limits of the <br> PLL is.<br> <br> Looks like we just forgot to apply that patch to amdgpu.<br> <br> Regards,<br> Christian.<br> <br> ><br> > Regards<br> > Shashank<br> > -----Original Message-----<br> > From: Koenig, Christian <a href="mailto:Christian.Koenig@amd.com"><Christian.Koenig@amd.com></a><br> > Sent: Wednesday, November 4, 2020 3:35 PM<br> > To: Sharma, Shashank <a href="mailto:Shashank.Sharma@amd.com"><Shashank.Sharma@amd.com></a>; <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a><br> > Cc: Deucher, Alexander <a href="mailto:Alexander.Deucher@amd.com"><Alexander.Deucher@amd.com></a>; Qin, Eddy <a href="mailto:Eddy.Qin@amd.com"><Eddy.Qin@amd.com></a><br> > Subject: Re: [PATCH] drm/amdgpu: clip the ref divider max value at 100<br> ><br> > Am 03.11.20 um 18:13 schrieb Shashank Sharma:<br> >> This patch limits the ref_div_max value to 100, during the calculation<br> >> of PLL feedback reference divider. With current value (128), the<br> >> produced fb_ref_div value generates unstable output at particular<br> >> frequencies. Radeon driver limits this value at 100.<br> > Mhm, is that 100 hard coded in radeon? I have no idea where that is coming from.<br> ><br> > Best would probably to grab a hardware engineer and try to figure out what the real maximums for the PLL is to still produce a stable signal.<br> ><br> > Christian.<br> ><br> >> On Oland, when we try to setup mode 2048x1280@60 (a bit weird, I<br> >> know), it demands a clock of 221270 Khz. It's been observed that the<br> >> PLL calculations using values 128 and 100 are vastly different, and<br> >> look like this:<br> >><br> >> +------------------------------------------+<br> >> |Parameter |AMDGPU |Radeon |<br> >> | | | |<br> >> +-------------+----------------------------+<br> >> |Clock feedback | |<br> >> |divider max | 128 | 100 |<br> >> |cap value | | |<br> >> | | | |<br> >> | | | |<br> >> +------------------------------------------+<br> >> |ref_div_max | | |<br> >> | | 42 | 20 |<br> >> | | | |<br> >> | | | |<br> >> +------------------------------------------+<br> >> |ref_div | 42 | 20 |<br> >> | | | |<br> >> +------------------------------------------+<br> >> |fb_div | 10326 | 8195 |<br> >> +------------------------------------------+<br> >> |fb_div | 1024 | 163 |<br> >> +------------------------------------------+<br> >> |fb_dev_p | 4 | 9 |<br> >> |frac fb_de^_p| | |<br> >> +----------------------------+-------------+<br> >><br> >> With ref_div_max value clipped at 100, AMDGPU driver can also drive<br> >> videmode 2048x1280@60 (221Mhz) and produce proper output without any<br> >> blanking and distortion on the screen.<br> >><br> >> PS: This value was changed from 128 to 100 in Radeon driver also, here:<br> >> <a href="https://github.com/freedesktop/drm-tip/commit/4b21ce1b4b5d262e7d4656b8"> https://github.com/freedesktop/drm-tip/commit/4b21ce1b4b5d262e7d4656b8</a><br> >> ececc891fc3cb806<br> >><br> >> Cc: Alex Deucher <a href="mailto:Alexander.Deucher@amd.com"><Alexander.Deucher@amd.com></a><br> >> Cc: Christian König <a href="mailto:christian.koenig@amd.com"><christian.koenig@amd.com></a><br> >> Cc: Eddy Qin <a href="mailto:Eddy.Qin@amd.com"><Eddy.Qin@amd.com></a><br> >><br> >> Signed-off-by: Shashank Sharma <a href="mailto:shashank.sharma@amd.com"><shashank.sharma@amd.com></a><br> >> ---<br> >> drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c | 2 +-<br> >> 1 file changed, 1 insertion(+), 1 deletion(-)<br> >><br> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c<br> >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c<br> >> index 1f2305b7bd13..23a2e1ebf78a 100644<br> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c<br> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c<br> >> @@ -85,7 +85,7 @@ static void amdgpu_pll_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_<br> >> unsigned *fb_div, unsigned *ref_div)<br> >> {<br> >> /* limit reference * post divider to a maximum */<br> >> - ref_div_max = min(128 / post_div, ref_div_max);<br> >> + ref_div_max = min(100 / post_div, ref_div_max);<br> >> <br> >> /* get matching reference and feedback divider */<br> >> *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u),<br> >> ref_div_max);<o:p></o:p></p> </div> </div> </blockquote> </div> </blockquote> <p class="MsoNormal"><o:p> </o:p></p> </div> </div> </body> </html>