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[AMD Official Use Only - Internal Distribution Only]<br>
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ping!<br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Zhao, Jiange <jianzh@amd.com><br>
<b>Sent:</b> Wednesday, November 25, 2020 10:10 PM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Min, Frank <Frank.Min@amd.com>; Chen, Horace <Horace.Chen@amd.com>; Zhang, Andy <Andy.Zhang@amd.com>; Zhao, Jiange <Jiange.Zhao@amd.com><br>
<b>Subject:</b> [PATCH] drm/amdgpu/SRIOV: Extend VF reset request wait period</font>
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<div class="PlainText">From: Jiange Zhao <Jiange.Zhao@amd.com><br>
<br>
In Virtualization case, when one VF is sending too many<br>
FLR requests, hypervisor would stop responding to this<br>
VF's request for a long period of time. This is called<br>
event guard. During this period of cooling time, guest<br>
driver should wait instead of doing other things. After<br>
this period of time, guest driver would resume reset<br>
process and return to normal.<br>
<br>
Currently, guest driver would wait 12 seconds and return fail<br>
if it doesn't get response from host.<br>
<br>
Solution: extend this waiting time in guest driver and poll<br>
response periodically.<br>
<br>
Signed-off-by: Jiange Zhao <Jiange.Zhao@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 11 ++++++++++-<br>
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h | 2 +-<br>
drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c | 11 ++++++++++-<br>
3 files changed, 21 insertions(+), 3 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c<br>
index f5ce9a9f4cf5..d8d8c623bb74 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c<br>
@@ -187,7 +187,16 @@ static int xgpu_ai_send_access_requests(struct amdgpu_device *adev,<br>
<br>
static int xgpu_ai_request_reset(struct amdgpu_device *adev)<br>
{<br>
- return xgpu_ai_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS);<br>
+ int ret, i = 0;<br>
+<br>
+ while (i < 11) {<br>
+ ret = xgpu_ai_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS);<br>
+ if (!ret)<br>
+ break;<br>
+ i++;<br>
+ }<br>
+<br>
+ return ret;<br>
}<br>
<br>
static int xgpu_ai_request_full_gpu_access(struct amdgpu_device *adev,<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h<br>
index 83b453f5d717..20ee2142f9ed 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h<br>
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h<br>
@@ -25,7 +25,7 @@<br>
#define __MXGPU_AI_H__<br>
<br>
#define AI_MAILBOX_POLL_ACK_TIMEDOUT 500<br>
-#define AI_MAILBOX_POLL_MSG_TIMEDOUT 12000<br>
+#define AI_MAILBOX_POLL_MSG_TIMEDOUT 6000<br>
#define AI_MAILBOX_POLL_FLR_TIMEDOUT 5000<br>
<br>
enum idh_request {<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c<br>
index 666ed99cc14b..0147dfe21a39 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c<br>
@@ -200,7 +200,16 @@ static int xgpu_nv_send_access_requests(struct amdgpu_device *adev,<br>
<br>
static int xgpu_nv_request_reset(struct amdgpu_device *adev)<br>
{<br>
- return xgpu_nv_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS);<br>
+ int ret, i = 0;<br>
+<br>
+ while (i < 11) {<br>
+ ret = xgpu_nv_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS);<br>
+ if (!ret)<br>
+ break;<br>
+ i++;<br>
+ }<br>
+<br>
+ return ret;<br>
}<br>
<br>
static int xgpu_nv_request_full_gpu_access(struct amdgpu_device *adev,<br>
-- <br>
2.25.1<br>
<br>
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