<html> <head> <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1"> <style type="text/css" style="display:none;"> P {margin-top:0;margin-bottom:0;} </style> </head> <body dir="ltr"> [AMD Official Use Only - Internal Distribution Only] <div> <div style="font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);"> </div> <hr tabindex="-1" style="display:inline-block; width:98%"> <div id="divRplyFwdMsg" dir="ltr">From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Xiaomeng Hou <Xiaomeng.Hou@amd.com> Sent: Tuesday, December 8, 2020 7:19 PM To: amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Huang, Ray <Ray.Huang@amd.com>; Hou, Xiaomeng (Matthew) <Xiaomeng.Hou@amd.com>; Quan, Evan <Evan.Quan@amd.com> Subject: [PATCH 2/3] drm/amd/pm: add interface to notify RLC status for vangogh <div> </div> </div> <div class="BodyFragment"> <div class="PlainText">Add this interface to notify PMFW the status (Normal/Off) of RLC engine. Before notify RLC status normal, need check its current status first. Send the message only when current status is still off. Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Change-Id: I2f1a7de23df7315a7b220ba6d0a4bcaa75c93fea --- drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 1 + .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 24 ++++++++++++++++++- .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h | 4 ++++ drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 13 ++++++++++ drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h | 2 ++ drivers/gpu/drm/amd/pm/swsmu/smu_internal.h | 1 + 6 files changed, 44 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h index 89be49a43500..0da00a92b478 100644 --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h @@ -583,6 +583,7 @@ struct pptable_funcs { int (*gpo_control)(struct smu_context *smu, bool enablement); int (*gfx_state_change_set)(struct smu_context *smu, uint32_t state); int (*set_fine_grain_gfx_freq_parameters)(struct smu_context *smu); + int (*notify_rlc_status)(struct smu_context *smu, uint32_t status); }; typedef enum { diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c index ddaa6a705fa6..03c2cd7a52a9 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c @@ -64,7 +64,7 @@ static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = { MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 0), MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), - MSG_MAP(Spare, PPSMC_MSG_spare, 0), + MSG_MAP(RlcPowerNotify, PPSMC_MSG_RlcPowerNotify, 0), MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 0), MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk, 0), MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 0), @@ -722,6 +722,27 @@ static int vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context *smu) return 0; } +static int vangogh_notify_rlc_status(struct smu_context *smu, uint32_t status) +{ + int ret = 0; + + switch (status) + { + case RLC_STATUS_OFF: + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RlcPowerNotify, status, NULL); + break; + case RLC_STATUS_NORMAL: + if (smu_cmn_get_rlc_status(smu) == 0) + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RlcPowerNotify, status, NULL); + break; + default: + dev_err(smu->adev->dev, "Unknown rlc status\n"); + return -EINVAL; + } + + return ret; +} + static const struct pptable_funcs vangogh_ppt_funcs = { .check_fw_status = smu_v11_0_check_fw_status, @@ -750,6 +771,7 @@ static const struct pptable_funcs vangogh_ppt_funcs = { .print_clk_levels = vangogh_print_fine_grain_clk, .set_default_dpm_table = vangogh_set_default_dpm_tables, .set_fine_grain_gfx_freq_parameters = vangogh_set_fine_grain_gfx_freq_parameters, + .notify_rlc_status = vangogh_notify_rlc_status, }; void vangogh_set_ppt_funcs(struct smu_context *smu) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h index 8756766296cd..eab455493076 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h @@ -32,4 +32,8 @@ extern void vangogh_set_ppt_funcs(struct smu_context *smu); #define VANGOGH_UMD_PSTATE_SOCCLK 678 #define VANGOGH_UMD_PSTATE_FCLK 800 +/* RLC Power Status */ +#define RLC_STATUS_OFF 0 +#define RLC_STATUS_NORMAL 1 + #endif diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c index f8260769061c..2f3e66b03dd2 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c @@ -42,6 +42,9 @@ * They share the same definitions and values. That makes common * APIs for SMC messages issuing for all ASICs possible. */ +#define mmMP1_SMN_C2PMSG_63 0x027f +#define mmMP1_SMN_C2PMSG_63_BASE_IDX 0 + #define mmMP1_SMN_C2PMSG_66 0x0282 #define mmMP1_SMN_C2PMSG_66_BASE_IDX 0 @@ -731,3 +734,13 @@ int smu_cmn_get_metrics_table(struct smu_context *smu, return ret; } + +int smu_cmn_get_rlc_status(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + uint32_t val; + + val = RREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_63); + + return val; +}</div> <div class="PlainText"> </div> <div class="PlainText">[kevin]:</div> <div class="PlainText"> </div> <div class="PlainText">these are not common code for whole smu driver, please move it to ppt.c file.</div> <div class="PlainText"> \ No newline at end of file diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h index 01e825d83d8d..7584089ef15f 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h @@ -95,5 +95,7 @@ int smu_cmn_get_metrics_table(struct smu_context *smu, void *metrics_table, bool bypass_cache); +int smu_cmn_get_rlc_status(struct smu_context *smu); + #endif #endif diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h index 68d9464ababc..8ef3713f7f3c 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h @@ -91,6 +91,7 @@ #define smu_post_init(smu) smu_ppt_funcs(post_init, 0, smu) #define smu_gpo_control(smu, enablement) smu_ppt_funcs(gpo_control, 0, smu, enablement) #define smu_set_fine_grain_gfx_freq_parameters(smu) smu_ppt_funcs(set_fine_grain_gfx_freq_parameters, 0, smu) +#define smu_notify_rlc_status(smu, status) smu_ppt_funcs(notify_rlc_status, 0, smu, status) #endif #endif -- 2.17.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org <a href="https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7CKevin1.Wang%40amd.com%7Cf740746f29d14d4777e808d89b6b4971%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637430232414406734%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=VPGv9GuTb22ZkzKp98iG3ibpG7BSwKaw%2FBT%2F6DFDnSs%3D&reserved=0">https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7CKevin1.Wang%40amd.com%7Cf740746f29d14d4777e808d89b6b4971%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637430232414406734%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=VPGv9GuTb22ZkzKp98iG3ibpG7BSwKaw%2FBT%2F6DFDnSs%3D&reserved=0</a> </div> </div> </div> </body> </html>