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[AMD Official Use Only - Internal Distribution Only]<br>
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Acked-by: Alex Deucher <alexander.deucher@amd.com><br>
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<div id="divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" face="Calibri, sans-serif" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Changfeng.Zhu <changfeng.zhu@amd.com><br>
<b>Sent:</b> Tuesday, December 8, 2020 9:06 PM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>; Huang, Ray <Ray.Huang@amd.com><br>
<b>Cc:</b> Zhu, Changfeng <Changfeng.Zhu@amd.com><br>
<b>Subject:</b> [PATCH] drm/amd/pm: update smu10.h WORKLOAD_PPLIB setting for raven</font>
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<div class="PlainText">From: changzhu <Changfeng.Zhu@amd.com><br>
<br>
From: Changfeng <Changfeng.Zhu@amd.com><br>
<br>
When using old WORKLOAD_PPLIB setting in smu10.h, there is problem that<br>
it can't be able to switch to mak gpu clk during compute workload.<br>
It needs to update WORKLOAD_PPLIB setting to fix this issue.<br>
<br>
Change-Id: Id2160a7b4a6cb8808d100de25e999714a7ccaebd<br>
Signed-off-by: Changfeng <Changfeng.Zhu@amd.com><br>
---<br>
drivers/gpu/drm/amd/pm/inc/smu10.h | 14 ++++++--------<br>
.../gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 9 +++------<br>
2 files changed, 9 insertions(+), 14 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/pm/inc/smu10.h b/drivers/gpu/drm/amd/pm/inc/smu10.h<br>
index b96520528240..9e837a5014c5 100644<br>
--- a/drivers/gpu/drm/amd/pm/inc/smu10.h<br>
+++ b/drivers/gpu/drm/amd/pm/inc/smu10.h<br>
@@ -136,14 +136,12 @@<br>
#define FEATURE_CORE_CSTATES_MASK (1 << FEATURE_CORE_CSTATES_BIT)<br>
<br>
/* Workload bits */<br>
-#define WORKLOAD_DEFAULT_BIT 0<br>
-#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1<br>
-#define WORKLOAD_PPLIB_POWER_SAVING_BIT 2<br>
-#define WORKLOAD_PPLIB_VIDEO_BIT 3<br>
-#define WORKLOAD_PPLIB_VR_BIT 4<br>
-#define WORKLOAD_PPLIB_COMPUTE_BIT 5<br>
-#define WORKLOAD_PPLIB_CUSTOM_BIT 6<br>
-#define WORKLOAD_PPLIB_COUNT 7<br>
+#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0<br>
+#define WORKLOAD_PPLIB_VIDEO_BIT 2<br>
+#define WORKLOAD_PPLIB_VR_BIT 3<br>
+#define WORKLOAD_PPLIB_COMPUTE_BIT 4<br>
+#define WORKLOAD_PPLIB_CUSTOM_BIT 5<br>
+#define WORKLOAD_PPLIB_COUNT 6<br>
<br>
typedef struct {<br>
/* MP1_EXT_SCRATCH0 */<br>
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c<br>
index 04226b1544e4..e57e64bbacdc 100644<br>
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c<br>
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c<br>
@@ -1298,15 +1298,9 @@ static int conv_power_profile_to_pplib_workload(int power_profile)<br>
int pplib_workload = 0;<br>
<br>
switch (power_profile) {<br>
- case PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT:<br>
- pplib_workload = WORKLOAD_DEFAULT_BIT;<br>
- break;<br>
case PP_SMC_POWER_PROFILE_FULLSCREEN3D:<br>
pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;<br>
break;<br>
- case PP_SMC_POWER_PROFILE_POWERSAVING:<br>
- pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT;<br>
- break;<br>
case PP_SMC_POWER_PROFILE_VIDEO:<br>
pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;<br>
break;<br>
@@ -1316,6 +1310,9 @@ static int conv_power_profile_to_pplib_workload(int power_profile)<br>
case PP_SMC_POWER_PROFILE_COMPUTE:<br>
pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;<br>
break;<br>
+ case PP_SMC_POWER_PROFILE_CUSTOM:<br>
+ pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT;<br>
+ break;<br>
}<br>
<br>
return pplib_workload;<br>
-- <br>
2.17.1<br>
<br>
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