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[AMD Official Use Only - Internal Distribution Only]<br>
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Acked-by: Alex Deucher <alexander.deucher@amd.com><br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Quan, Evan <Evan.Quan@amd.com><br>
<b>Sent:</b> Wednesday, December 9, 2020 1:35 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Deucher, Alexander <Alexander.Deucher@amd.com>; Quan, Evan <Evan.Quan@amd.com><br>
<b>Subject:</b> [PATCH] drm/amd/pm: fulfill the sienna cichlid UMD PSTATE profiling clocks</font>
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<div class="PlainText">Fulfill the UMD PSTATE profiling clocks of sienna cichlid.<br>
<br>
Change-Id: Ib9078c73d3fbd786080449255645ae8b9f879092<br>
Signed-off-by: Evan Quan <evan.quan@amd.com><br>
---<br>
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 6 ++++++<br>
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.h | 4 ++++<br>
2 files changed, 10 insertions(+)<br>
<br>
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c<br>
index 74cf027e4a41..3fb70cac72ea 100644<br>
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c<br>
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c<br>
@@ -1341,12 +1341,18 @@ static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)<br>
<br>
pstate_table->gfxclk_pstate.min = gfx_table->min;<br>
pstate_table->gfxclk_pstate.peak = gfx_table->max;<br>
+ if (gfx_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK)<br>
+ pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;<br>
<br>
pstate_table->uclk_pstate.min = mem_table->min;<br>
pstate_table->uclk_pstate.peak = mem_table->max;<br>
+ if (mem_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK)<br>
+ pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;<br>
<br>
pstate_table->socclk_pstate.min = soc_table->min;<br>
pstate_table->socclk_pstate.peak = soc_table->max;<br>
+ if (soc_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK)<br>
+ pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;<br>
<br>
return 0;<br>
}<br>
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.h<br>
index 57e120c440ea..38cd0ece24f6 100644<br>
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.h<br>
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.h<br>
@@ -29,6 +29,10 @@ typedef enum {<br>
POWER_SOURCE_COUNT,<br>
} POWER_SOURCE_e;<br>
<br>
+#define SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK 1825<br>
+#define SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK 960<br>
+#define SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK 1000<br>
+<br>
extern void sienna_cichlid_set_ppt_funcs(struct smu_context *smu);<br>
<br>
#endif<br>
-- <br>
2.29.0<br>
<br>
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