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[AMD Official Use Only - Internal Distribution Only]<br>
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Acked-by: Alex Deucher <alexander.deucher@amd.com><br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Hawking Zhang <Hawking.Zhang@amd.com><br>
<b>Sent:</b> Tuesday, December 22, 2020 6:10 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>; Sierra Guiza, Alejandro (Alex) <Alex.Sierra@amd.com>; Jian, Jane <Jane.Jian@amd.com><br>
<b>Cc:</b> Zhang, Hawking <Hawking.Zhang@amd.com><br>
<b>Subject:</b> [PATCH] drm/amdgpu: drop psp ih programming for sriov guest on navi</font>
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<div class="PlainText">the psp access ih path is not needed in navi<br>
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Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com><br>
Change-Id: Ib68bfb1b13e1cec03ec27bc9a867e2b37fc2fc8a<br>
---<br>
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 18 ++----------------<br>
1 file changed, 2 insertions(+), 16 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c<br>
index 060357625504..f4e4040bbd25 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c<br>
@@ -151,14 +151,7 @@ static int navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev,<br>
/* enable_intr field is only valid in ring0 */<br>
if (ih == &adev->irq.ih)<br>
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));<br>
- if (amdgpu_sriov_vf(adev)) {<br>
- if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {<br>
- dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n");<br>
- return -ETIMEDOUT;<br>
- }<br>
- } else {<br>
- WREG32(ih_regs->ih_rb_cntl, tmp);<br>
- }<br>
+ WREG32(ih_regs->ih_rb_cntl, tmp);<br>
<br>
if (enable) {<br>
ih->enabled = true;<br>
@@ -268,14 +261,7 @@ static int navi10_ih_enable_ring(struct amdgpu_device *adev,<br>
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);<br>
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);<br>
}<br>
- if (amdgpu_sriov_vf(adev)) {<br>
- if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {<br>
- dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n");<br>
- return -ETIMEDOUT;<br>
- }<br>
- } else {<br>
- WREG32(ih_regs->ih_rb_cntl, tmp);<br>
- }<br>
+ WREG32(ih_regs->ih_rb_cntl, tmp);<br>
<br>
if (ih == &adev->irq.ih) {<br>
/* set the ih ring 0 writeback address whether it's enabled or not */<br>
-- <br>
2.17.1<br>
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