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[AMD Official Use Only - Internal Distribution Only]<br>
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[Why] the initial purpose of dcn10 pipe split is to support
<div>some high bandwidth mode which requires dispclk greater</div>
<div>than max dispclk. By initial bring up power measurement</div>
<div>data, it showed power consumption is less with pipe split</div>
<div>for dcn block. This could be reason for enable pipe split</div>
<div>by default. By battery life measurement of some Chromebooks,</div>
<div>result shows battery life is longer with pipe split disabled.</div>
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<div>[How] disable pipe split by default. Pipe split could be</div>
<div>still enabled when required dispclk is greater than max dispclk.</div>
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<div>Signed-off-by: hersen wu <hersenxs.wu@amd.com></div>
<div>---</div>
<div> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 4 ++--</div>
<div> 1 file changed, 2 insertions(+), 2 deletions(-)</div>
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<div>diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c</div>
<div>index bdc37831535e..17eafe209946 100644</div>
<div>--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c</div>
<div>+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c</div>
<div>@@ -608,8 +608,8 @@ static const struct dc_debug_options debug_defaults_drv = {</div>
<div> .disable_pplib_clock_request = false,</div>
<div> .disable_pplib_wm_range = false,</div>
<div> .pplib_wm_report_mode = WM_REPORT_DEFAULT,</div>
<div>- .pipe_split_policy = MPC_SPLIT_DYNAMIC,</div>
<div>- .force_single_disp_pipe_split = true,</div>
<div>+ .pipe_split_policy = MPC_SPLIT_AVOID,</div>
<div>+ .force_single_disp_pipe_split = false,</div>
<div> .disable_dcc = DCC_ENABLE,</div>
<div> .voltage_align_fclk = true,</div>
<div> .disable_stereo_support = true,</div>
<div>-- </div>
<div>2.17.1</div>
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