<div dir="ltr">Hi,<div><br></div><div>This update doesn't match the gc_9_0_0 headers from the drm-next branch as such cannot be made to umr. You need to first update the kernel headers and then we circle back to umr.</div><div><br></div><div>Tom</div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Tue, Jan 26, 2021 at 12:43 AM <<a href="mailto:raykwok1150@163.com">raykwok1150@163.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">From: Guo Lei <<a href="mailto:raykwok1150@163.com" target="_blank">raykwok1150@163.com</a>><br>
<br>
sync form drm-next<br>
<br>
Signed-off-by: Guo Lei <<a href="mailto:raykwok1150@163.com" target="_blank">raykwok1150@163.com</a>><br>
---<br>
src/lib/ip/gfx90_bits.i | 7 ++-----<br>
src/lib/ip/gfx90_regs.i | 2 +-<br>
2 files changed, 3 insertions(+), 6 deletions(-)<br>
<br>
diff --git a/src/lib/ip/gfx90_bits.i b/src/lib/ip/gfx90_bits.i<br>
index 6741947..8aabb8a 100644<br>
--- a/src/lib/ip/gfx90_bits.i<br>
+++ b/src/lib/ip/gfx90_bits.i<br>
@@ -8711,11 +8711,8 @@ static struct umr_bitfield mmGC_CAC_CTRL_2[] = {<br>
{ "CAC_SOFT_CTRL_ENABLE", 1, 1, &umr_bitfield_default },<br>
{ "UNUSED_0", 2, 31, &umr_bitfield_default },<br>
};<br>
-static struct umr_bitfield mmGC_CAC_CGTT_CLK_CTRL[] = {<br>
- { "ON_DELAY", 0, 3, &umr_bitfield_default },<br>
- { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },<br>
- { "SOFT_OVERRIDE_DYN", 30, 30, &umr_bitfield_default },<br>
- { "SOFT_OVERRIDE_REG", 31, 31, &umr_bitfield_default },<br>
+static struct umr_bitfield mmGC_CAC_INDEX_AUTO_INCR_EN[] = {<br>
+ { "GC_CAC_INDEX_AUTO_INCR_EN", 0, 0, &umr_bitfield_default },<br>
};<br>
static struct umr_bitfield mmGC_CAC_AGGR_LOWER[] = {<br>
{ "AGGR_31_0", 0, 31, &umr_bitfield_default },<br>
diff --git a/src/lib/ip/gfx90_regs.i b/src/lib/ip/gfx90_regs.i<br>
index 1342a66..a9ef9c6 100644<br>
--- a/src/lib/ip/gfx90_regs.i<br>
+++ b/src/lib/ip/gfx90_regs.i<br>
@@ -1418,7 +1418,7 @@<br>
{ "mmDIDT_IND_DATA", REG_MMIO, 0x1281, 0, &mmDIDT_IND_DATA[0], sizeof(mmDIDT_IND_DATA)/sizeof(mmDIDT_IND_DATA[0]), 0, 0 },<br>
{ "mmGC_CAC_CTRL_1", REG_MMIO, 0x1284, 0, &mmGC_CAC_CTRL_1[0], sizeof(mmGC_CAC_CTRL_1)/sizeof(mmGC_CAC_CTRL_1[0]), 0, 0 },<br>
{ "mmGC_CAC_CTRL_2", REG_MMIO, 0x1285, 0, &mmGC_CAC_CTRL_2[0], sizeof(mmGC_CAC_CTRL_2)/sizeof(mmGC_CAC_CTRL_2[0]), 0, 0 },<br>
- { "mmGC_CAC_CGTT_CLK_CTRL", REG_MMIO, 0x1286, 0, &mmGC_CAC_CGTT_CLK_CTRL[0], sizeof(mmGC_CAC_CGTT_CLK_CTRL)/sizeof(mmGC_CAC_CGTT_CLK_CTRL[0]), 0, 0 },<br>
+ { "mmGC_CAC_INDEX_AUTO_INCR_EN", REG_MMIO, 0x1286, 0, &mmGC_CAC_INDEX_AUTO_INCR_EN[0], sizeof(mmGC_CAC_INDEX_AUTO_INCR_EN)/sizeof(mmGC_CAC_INDEX_AUTO_INCR_EN[0]), 0, 0 },<br>
{ "mmGC_CAC_AGGR_LOWER", REG_MMIO, 0x1287, 0, &mmGC_CAC_AGGR_LOWER[0], sizeof(mmGC_CAC_AGGR_LOWER)/sizeof(mmGC_CAC_AGGR_LOWER[0]), 0, 0 },<br>
{ "mmGC_CAC_AGGR_UPPER", REG_MMIO, 0x1288, 0, &mmGC_CAC_AGGR_UPPER[0], sizeof(mmGC_CAC_AGGR_UPPER)/sizeof(mmGC_CAC_AGGR_UPPER[0]), 0, 0 },<br>
{ "mmGC_CAC_SOFT_CTRL", REG_MMIO, 0x128d, 0, &mmGC_CAC_SOFT_CTRL[0], sizeof(mmGC_CAC_SOFT_CTRL)/sizeof(mmGC_CAC_SOFT_CTRL[0]), 0, 0 },<br>
-- <br>
2.17.1<br>
<br>
<br>
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</blockquote></div>