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    <div class="moz-cite-prefix">The alternative is to wait till
      drm-misc-next is merged into drm-next, then rebase
      amd-staging-drm-next on top of that (or directly drm-misc-next)
      and push then.<br>
      <br>
      Would give us at least a clean history. Question is rather if we
      want it in 5.12?<br>
      <br>
      Christian.<br>
      <br>
      Am 05.02.21 um 15:50 schrieb Deucher, Alexander:<br>
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        [AMD Official Use Only - Internal Distribution Only]<br>
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          Good question.  I think push it to drm-misc-next for
          upstream.  We can carry it internally in amd-staging-drm-next
          for internal testing and I can coordinate with drm-next.  I
          think the amdgpu changes are pretty straightforward, so
          shouldn't be too hard keep the merge straight.  I dunno.  <br>
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          Alex</div>
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        <div id="divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" face="Calibri, sans-serif" color="#000000"><b>From:</b>
            Christian König <a class="moz-txt-link-rfc2396E" href="mailto:ckoenig.leichtzumerken@gmail.com"><ckoenig.leichtzumerken@gmail.com></a><br>
            <b>Sent:</b> Friday, February 5, 2021 4:58 AM<br>
            <b>To:</b> Liu, Leo <a class="moz-txt-link-rfc2396E" href="mailto:Leo.Liu@amd.com"><Leo.Liu@amd.com></a>;
            <a class="moz-txt-link-abbreviated" href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a>
            <a class="moz-txt-link-rfc2396E" href="mailto:amd-gfx@lists.freedesktop.org"><amd-gfx@lists.freedesktop.org></a>;
            <a class="moz-txt-link-abbreviated" href="mailto:dri-devel@lists.freedesktop.org">dri-devel@lists.freedesktop.org</a>
            <a class="moz-txt-link-rfc2396E" href="mailto:dri-devel@lists.freedesktop.org"><dri-devel@lists.freedesktop.org></a>; Deucher, Alexander
            <a class="moz-txt-link-rfc2396E" href="mailto:Alexander.Deucher@amd.com"><Alexander.Deucher@amd.com></a><br>
            <b>Subject:</b> Re: [PATCH 3/3] drm/amdgpu: share scheduler
            score on VCN3 instances</font>
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              <div class="PlainText">Alex how do we want to merge this?<br>
                <br>
                I've just pushed the first patch to drm-misc-next since
                that needed a <br>
                rebase because it touches other drivers as well.<br>
                <br>
                But the rest is really AMD specific and I'm not sure if
                the dependent <br>
                stuff is already in there as well.<br>
                <br>
                So if I push it to drm-misc-next you will probably need
                to merge and if <br>
                I push it to amd-staging-drm-next somebody else might
                need to merge when <br>
                drm-misc-next is merged.<br>
                <br>
                Ideas?<br>
                <br>
                Christian.<br>
                <br>
                Am 04.02.21 um 19:34 schrieb Leo Liu:<br>
                > The series are:<br>
                ><br>
                > Reviewed-and-Tested-by: Leo Liu
                <a class="moz-txt-link-rfc2396E" href="mailto:leo.liu@amd.com"><leo.liu@amd.com></a><br>
                ><br>
                ><br>
                > On 2021-02-04 9:44 a.m., Christian König wrote:<br>
                >> The VCN3 instances can do both decode as well
                as encode.<br>
                >><br>
                >> Share the scheduler load balancing score and
                remove fixing encode to<br>
                >> only the second instance.<br>
                >><br>
                >> Signed-off-by: Christian König
                <a class="moz-txt-link-rfc2396E" href="mailto:christian.koenig@amd.com"><christian.koenig@amd.com></a><br>
                >> ---<br>
                >>   drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h |  1
                +<br>
                >>   drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c   | 11
                +++++++----<br>
                >>   2 files changed, 8 insertions(+), 4
                deletions(-)<br>
                >><br>
                >> diff --git
                a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h <br>
                >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h<br>
                >> index 13aa417f6be7..d10bc4f0a05f 100644<br>
                >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h<br>
                >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h<br>
                >> @@ -211,6 +211,7 @@ struct amdgpu_vcn_inst {<br>
                >>       void            *saved_bo;<br>
                >>       struct amdgpu_ring    ring_dec;<br>
                >>       struct amdgpu_ring   
                ring_enc[AMDGPU_VCN_MAX_ENC_RINGS];<br>
                >> +    atomic_t        sched_score;<br>
                >>       struct amdgpu_irq_src    irq;<br>
                >>       struct amdgpu_vcn_reg    external;<br>
                >>       struct amdgpu_bo    *dpg_sram_bo;<br>
                >> diff --git
                a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c <br>
                >> b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c<br>
                >> index 239a4eb52c61..b33f513fd2ac 100644<br>
                >> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c<br>
                >> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c<br>
                >> @@ -171,6 +171,7 @@ static int
                vcn_v3_0_sw_init(void *handle)<br>
                >>         for (i = 0; i <
                adev->vcn.num_vcn_inst; i++) {<br>
                >>           volatile struct amdgpu_fw_shared
                *fw_shared;<br>
                >> +<br>
                >>           if (adev->vcn.harvest_config &
                (1 << i))<br>
                >>               continue;<br>
                >>   @@ -198,6 +199,8 @@ static int
                vcn_v3_0_sw_init(void *handle)<br>
                >>           if (r)<br>
                >>               return r;<br>
                >>   +       
                atomic_set(&adev->vcn.inst[i].sched_score, 0);<br>
                >> +<br>
                >>           ring =
                &adev->vcn.inst[i].ring_dec;<br>
                >>           ring->use_doorbell = true;<br>
                >>           if (amdgpu_sriov_vf(adev)) {<br>
                >> @@ -209,7 +212,8 @@ static int
                vcn_v3_0_sw_init(void *handle)<br>
                >>               ring->no_scheduler = true;<br>
                >>           sprintf(ring->name, "vcn_dec_%d",
                i);<br>
                >>           r = amdgpu_ring_init(adev, ring, 512,
                <br>
                >> &adev->vcn.inst[i].irq, 0,<br>
                >> -                     AMDGPU_RING_PRIO_DEFAULT,
                NULL);<br>
                >> +                     AMDGPU_RING_PRIO_DEFAULT,<br>
                >> +                    
                &adev->vcn.inst[i].sched_score);<br>
                >>           if (r)<br>
                >>               return r;<br>
                >>   @@ -227,11 +231,10 @@ static int
                vcn_v3_0_sw_init(void *handle)<br>
                >>               } else {<br>
                >>                   ring->doorbell_index = <br>
                >> (adev->doorbell_index.vcn.vcn_ring0_1
                << 1) + 2 + j + 8 * i;<br>
                >>               }<br>
                >> -            if (adev->asic_type ==
                CHIP_SIENNA_CICHLID && i != 1)<br>
                >> -                ring->no_scheduler = true;<br>
                >>               sprintf(ring->name,
                "vcn_enc_%d.%d", i, j);<br>
                >>               r = amdgpu_ring_init(adev, ring,
                512, <br>
                >> &adev->vcn.inst[i].irq, 0,<br>
                >> -                        
                AMDGPU_RING_PRIO_DEFAULT, NULL);<br>
                >> +                        
                AMDGPU_RING_PRIO_DEFAULT,<br>
                >> + &adev->vcn.inst[i].sched_score);<br>
                >>               if (r)<br>
                >>                   return r;<br>
                >>           }<br>
                <br>
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