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<p class="msipheader251902e5" style="margin:0in"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:#317100">[AMD Public Use]</span><o:p></o:p></p>
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<p class="MsoNormal">Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com><o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Regards,<br>
Hawking<o:p></o:p></p>
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<p class="MsoNormal"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org>
<b>On Behalf Of </b>Marek Ol¹įk<br>
<b>Sent:</b> Saturday, February 6, 2021 08:47<br>
<b>To:</b> amd-gfx mailing list <amd-gfx@lists.freedesktop.org><br>
<b>Subject:</b> [PATCH] drm/amdgpu: fix CGTS_TCC_DISABLE register offset on gfx10.3<o:p></o:p></p>
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<p class="MsoNormal">Please review.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Thanks,<o:p></o:p></p>
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<p class="MsoNormal">Marek<o:p></o:p></p>
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