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[AMD Official Use Only - Internal Distribution Only]<br>
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Acked-by: Alex Deucher <alexander.deucher@amd.com><br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Horace Chen <horace.chen@amd.com><br>
<b>Sent:</b> Friday, February 26, 2021 1:31 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Grodzovsky, Andrey <Andrey.Grodzovsky@amd.com>; Quan, Evan <Evan.Quan@amd.com>; Chen, Horace <Horace.Chen@amd.com>; Tuikov, Luben <Luben.Tuikov@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>;
 Xiao, Jack <Jack.Xiao@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; Liu, Monk <Monk.Liu@amd.com>; Xu, Feifei <Feifei.Xu@amd.com>; Wang, Kevin(Yang) <Kevin1.Wang@amd.com>; Xiaojie Yuan <xiaojie.yuan@amd.com><br>
<b>Subject:</b> [PATCH] drm/amdgpu: enable one vf mode on sienna cichlid vf</font>
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<div class="PlainText">sienna cichlid needs one vf mode which allows vf to set and get<br>
clock status from guest vm. So now expose the required interface<br>
and allow some smu request on VF mode. Also since this asic blocked<br>
direct MMIO access, use KIQ to send SMU request under sriov vf.<br>
<br>
OD use same command as getting pp table which is not allowed for<br>
 sienna cichlid, so remove OD feature under sriov vf.<br>
<br>
Signed-off-by: Horace Chen <horace.chen@amd.com><br>
---<br>
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c           |  2 ++<br>
 drivers/gpu/drm/amd/pm/amdgpu_pm.c                   |  2 +-<br>
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c            | 10 ++++++----<br>
 .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c  | 10 +++++-----<br>
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c               | 12 ++++++------<br>
 5 files changed, 20 insertions(+), 16 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c<br>
index f0f7ed42ee7f..dfbf2f2db0de 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c<br>
@@ -2043,6 +2043,8 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)<br>
         adev->pm.pp_feature = amdgpu_pp_feature_mask;<br>
         if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS)<br>
                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;<br>
+       if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)<br>
+               adev->pm.pp_feature &= ~PP_OVERDRIVE_MASK;<br>
 <br>
         for (i = 0; i < adev->num_ip_blocks; i++) {<br>
                 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {<br>
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c<br>
index b770dd634ab6..1866cbaf70c3 100644<br>
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c<br>
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c<br>
@@ -2167,7 +2167,7 @@ static ssize_t amdgpu_get_gpu_metrics(struct device *dev,<br>
 <br>
 static struct amdgpu_device_attr amdgpu_device_attrs[] = {<br>
         AMDGPU_DEVICE_ATTR_RW(power_dpm_state,                          ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),<br>
-       AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level,        ATTR_FLAG_BASIC),<br>
+       AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level,        ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),<br>
         AMDGPU_DEVICE_ATTR_RO(pp_num_states,                            ATTR_FLAG_BASIC),<br>
         AMDGPU_DEVICE_ATTR_RO(pp_cur_state,                             ATTR_FLAG_BASIC),<br>
         AMDGPU_DEVICE_ATTR_RW(pp_force_state,                           ATTR_FLAG_BASIC),<br>
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c<br>
index d143ef1b460b..7033d52eb4d0 100644<br>
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c<br>
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c<br>
@@ -612,10 +612,12 @@ static int smu_late_init(void *handle)<br>
                 return ret;<br>
         }<br>
 <br>
-       ret = smu_set_default_od_settings(smu);<br>
-       if (ret) {<br>
-               dev_err(adev->dev, "Failed to setup default OD settings!\n");<br>
-               return ret;<br>
+       if (smu->od_enabled) {<br>
+               ret = smu_set_default_od_settings(smu);<br>
+               if (ret) {<br>
+                       dev_err(adev->dev, "Failed to setup default OD settings!\n");<br>
+                       return ret;<br>
+               }<br>
         }<br>
 <br>
         ret = smu_populate_umd_state_clk(smu);<br>
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c<br>
index af73e1430af5..441effc23625 100644<br>
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c<br>
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c<br>
@@ -89,17 +89,17 @@ static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT]<br>
         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetRunningSmuFeaturesHigh,   1),<br>
         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask,             1),<br>
         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit,                 0),<br>
-       MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,       0),<br>
-       MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,        0),<br>
+       MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,       1),<br>
+       MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,        1),<br>
         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh,        0),<br>
         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow,         0),<br>
-       MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,       0),<br>
+       MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,       1),<br>
         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,       0),<br>
         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable,           0),<br>
         MSG_MAP(RunDcBtc,                       PPSMC_MSG_RunDcBtc,                    0),<br>
         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco,                   0),<br>
-       MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq,            0),<br>
-       MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq,            0),<br>
+       MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq,            1),<br>
+       MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq,            1),<br>
         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq,            1),<br>
         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq,            0),<br>
         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq,               1),<br>
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c<br>
index bcedd4d92e35..d955dc4c6998 100644<br>
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c<br>
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c<br>
@@ -73,7 +73,7 @@ static void smu_cmn_read_arg(struct smu_context *smu,<br>
 {<br>
         struct amdgpu_device *adev = smu->adev;<br>
 <br>
-       *arg = RREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_82);<br>
+       *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);<br>
 }<br>
 <br>
 static int smu_cmn_wait_for_response(struct smu_context *smu)<br>
@@ -82,7 +82,7 @@ static int smu_cmn_wait_for_response(struct smu_context *smu)<br>
         uint32_t cur_value, i, timeout = adev->usec_timeout * 10;<br>
 <br>
         for (i = 0; i < timeout; i++) {<br>
-               cur_value = RREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_90);<br>
+               cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);<br>
                 if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)<br>
                         return cur_value;<br>
 <br>
@@ -93,7 +93,7 @@ static int smu_cmn_wait_for_response(struct smu_context *smu)<br>
         if (i == timeout)<br>
                 return -ETIME;<br>
 <br>
-       return RREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_90);<br>
+       return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);<br>
 }<br>
 <br>
 int smu_cmn_send_msg_without_waiting(struct smu_context *smu,<br>
@@ -111,9 +111,9 @@ int smu_cmn_send_msg_without_waiting(struct smu_context *smu,<br>
                 return ret;<br>
         }<br>
 <br>
-       WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);<br>
-       WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_82, param);<br>
-       WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);<br>
+       WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);<br>
+       WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);<br>
+       WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);<br>
 <br>
         return 0;<br>
 }<br>
-- <br>
2.17.1<br>
<br>
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