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Hi Thomas,<br>
<br>
<div class="moz-cite-prefix">Am 03.03.21 um 09:49 schrieb Thomas
Zimmermann:<br>
</div>
<blockquote type="cite"
cite="mid:cff35ce0-3ad1-cc4a-f6ec-d423a913d0bc@suse.de">Hi
<br>
<br>
Am 01.03.21 um 23:43 schrieb Oak Zeng:
<br>
<blockquote type="cite">If tbo.mem.bus.caching is cached, buffer
is intended to be mapped
<br>
as cached from CPU. Map it with ioremap_cache.
<br>
</blockquote>
<br>
Just a question for my understanding: This is on-device memory?
Accessing device memory is usually slow. If that memory can be
mapped with CPU caching enabled, access will roughly be as fast as
for system memory?
<br>
</blockquote>
<br>
There is still a penalty associated with accessing it from the CPU,
but it is much faster (both lower latency as well as throughput) as
traditional device memory accessed over PCIe.<br>
<br>
Regards,<br>
Christian.<br>
<br>
<blockquote type="cite"
cite="mid:cff35ce0-3ad1-cc4a-f6ec-d423a913d0bc@suse.de">
<br>
Best regards
<br>
Thomas
<br>
<br>
<blockquote type="cite">
<br>
This wasn't necessary before as device memory was never mapped
<br>
as cached from CPU side. It becomes necessary for aldebaran as
<br>
device memory is mapped cached from CPU.
<br>
<br>
Signed-off-by: Oak Zeng <a class="moz-txt-link-rfc2396E" href="mailto:Oak.Zeng@amd.com"><Oak.Zeng@amd.com></a>
<br>
Reviewed-by: Christian Konig <a class="moz-txt-link-rfc2396E" href="mailto:Christian.Koenig@amd.com"><Christian.Koenig@amd.com></a>
<br>
---
<br>
drivers/gpu/drm/ttm/ttm_bo_util.c | 8 ++++++++
<br>
1 file changed, 8 insertions(+)
<br>
<br>
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c
b/drivers/gpu/drm/ttm/ttm_bo_util.c
<br>
index 031e581..8c65a13 100644
<br>
--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
<br>
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
<br>
@@ -91,6 +91,8 @@ static int ttm_resource_ioremap(struct
ttm_device *bdev,
<br>
if (mem->bus.caching == ttm_write_combined)
<br>
addr = ioremap_wc(mem->bus.offset, bus_size);
<br>
+ else if (mem->bus.caching == ttm_cached)
<br>
+ addr = ioremap_cache(mem->bus.offset, bus_size);
<br>
else
<br>
addr = ioremap(mem->bus.offset, bus_size);
<br>
if (!addr) {
<br>
@@ -372,6 +374,9 @@ static int ttm_bo_ioremap(struct
ttm_buffer_object *bo,
<br>
if (mem->bus.caching == ttm_write_combined)
<br>
map->virtual = ioremap_wc(bo->mem.bus.offset
+ offset,
<br>
size);
<br>
+ else if (mem->bus.caching == ttm_cached)
<br>
+ map->virtual =
ioremap_cache(bo->mem.bus.offset + offset,
<br>
+ size);
<br>
else
<br>
map->virtual = ioremap(bo->mem.bus.offset +
offset,
<br>
size);
<br>
@@ -490,6 +495,9 @@ int ttm_bo_vmap(struct ttm_buffer_object
*bo, struct dma_buf_map *map)
<br>
else if (mem->bus.caching == ttm_write_combined)
<br>
vaddr_iomem = ioremap_wc(mem->bus.offset,
<br>
bo->base.size);
<br>
+ else if (mem->bus.caching == ttm_cached)
<br>
+ vaddr_iomem = ioremap_cache(mem->bus.offset,
<br>
+ bo->base.size);
<br>
else
<br>
vaddr_iomem = ioremap(mem->bus.offset,
bo->base.size);
<br>
<br>
</blockquote>
<br>
<br>
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</blockquote>
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