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[AMD Official Use Only - Internal Distribution Only]<br>
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Reviewed-by: Alex Deucher <alexander.deucher@amd.com><br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Kenneth Feng <kenneth.feng@amd.com><br>
<b>Sent:</b> Thursday, March 11, 2021 1:58 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Feng, Kenneth <Kenneth.Feng@amd.com><br>
<b>Subject:</b> [PATCH v2] drm/amd/pm: workaround for audio noise issue</font>
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<div class="PlainText">On some Intel platforms, audio noise can be detected due to<br>
high pcie speed switch latency.<br>
This patch leaverages ppfeaturemask to fix to the highest pcie<br>
speed then disable pcie switching.<br>
<br>
v2:<br>
coding style fix<br>
<br>
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com><br>
---<br>
 .../drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c   | 54 ++++++++++++++<br>
 .../drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 74 ++++++++++++++++---<br>
 .../drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c | 24 ++++++<br>
 .../drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c | 25 +++++++<br>
 4 files changed, 166 insertions(+), 11 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c<br>
index a58f92249c53..54bbee310e57 100644<br>
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c<br>
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c<br>
@@ -587,6 +587,48 @@ static int smu7_force_switch_to_arbf0(struct pp_hwmgr *hwmgr)<br>
                         tmp, MC_CG_ARB_FREQ_F0);<br>
 }<br>
 <br>
+static uint16_t smu7_override_pcie_speed(struct pp_hwmgr *hwmgr)<br>
+{<br>
+       struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);<br>
+       uint16_t pcie_gen = 0;<br>
+<br>
+       if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 &&<br>
+           adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4)<br>
+               pcie_gen = 3;<br>
+       else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 &&<br>
+               adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3)<br>
+               pcie_gen = 2;<br>
+       else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 &&<br>
+               adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2)<br>
+               pcie_gen = 1;<br>
+       else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 &&<br>
+               adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1)<br>
+               pcie_gen = 0;<br>
+<br>
+       return pcie_gen;<br>
+}<br>
+<br>
+static uint16_t smu7_override_pcie_width(struct pp_hwmgr *hwmgr)<br>
+{<br>
+       struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);<br>
+       uint16_t pcie_width = 0;<br>
+<br>
+       if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)<br>
+               pcie_width = 16;<br>
+       else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)<br>
+               pcie_width = 12;<br>
+       else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)<br>
+               pcie_width = 8;<br>
+       else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)<br>
+               pcie_width = 4;<br>
+       else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)<br>
+               pcie_width = 2;<br>
+       else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)<br>
+               pcie_width = 1;<br>
+<br>
+       return pcie_width;<br>
+}<br>
+<br>
 static int smu7_setup_default_pcie_table(struct pp_hwmgr *hwmgr)<br>
 {<br>
         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);<br>
@@ -683,6 +725,11 @@ static int smu7_setup_default_pcie_table(struct pp_hwmgr *hwmgr)<br>
                                         PP_Min_PCIEGen),<br>
                         get_pcie_lane_support(data->pcie_lane_cap,<br>
                                         PP_Max_PCIELane));<br>
+<br>
+               if (data->pcie_dpm_key_disabled)<br>
+                       phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,<br>
+                               data->dpm_table.pcie_speed_table.count,<br>
+                               smu7_override_pcie_speed(hwmgr), smu7_override_pcie_width(hwmgr));<br>
         }<br>
         return 0;<br>
 }<br>
@@ -1248,6 +1295,13 @@ static int smu7_start_dpm(struct pp_hwmgr *hwmgr)<br>
                                                 NULL)),<br>
                                 "Failed to enable pcie DPM during DPM Start Function!",<br>
                                 return -EINVAL);<br>
+       } else {<br>
+               PP_ASSERT_WITH_CODE(<br>
+                               (0 == smum_send_msg_to_smc(hwmgr,<br>
+                                               PPSMC_MSG_PCIeDPM_Disable,<br>
+                                               NULL)),<br>
+                               "Failed to disble pcie DPM during DPM Start Function!",<br>
+                               return -EINVAL);<br>
         }<br>
 <br>
         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,<br>
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c<br>
index 408b35866704..f5a32654cde7 100644<br>
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c<br>
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c<br>
@@ -54,6 +54,9 @@<br>
 #include "smuio/smuio_9_0_offset.h"<br>
 #include "smuio/smuio_9_0_sh_mask.h"<br>
 <br>
+#define smnPCIE_LC_SPEED_CNTL                  0x11140290<br>
+#define smnPCIE_LC_LINK_WIDTH_CNTL             0x11140288<br>
+<br>
 #define HBM_MEMORY_CHANNEL_WIDTH    128<br>
 <br>
 static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};<br>
@@ -443,8 +446,7 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)<br>
         if (PP_CAP(PHM_PlatformCaps_VCEDPM))<br>
                 data->smu_features[GNLD_DPM_VCE].supported = true;<br>
 <br>
-       if (!data->registry_data.pcie_dpm_key_disabled)<br>
-               data->smu_features[GNLD_DPM_LINK].supported = true;<br>
+       data->smu_features[GNLD_DPM_LINK].supported = true;<br>
 <br>
         if (!data->registry_data.dcefclk_dpm_key_disabled)<br>
                 data->smu_features[GNLD_DPM_DCEFCLK].supported = true;<br>
@@ -1544,6 +1546,13 @@ static int vega10_override_pcie_parameters(struct pp_hwmgr *hwmgr)<br>
                         pp_table->PcieLaneCount[i] = pcie_width;<br>
         }<br>
 <br>
+       if (data->registry_data.pcie_dpm_key_disabled) {<br>
+               for (i = 0; i < NUM_LINK_LEVELS; i++) {<br>
+                       pp_table->PcieGenSpeed[i] = pcie_gen;<br>
+                       pp_table->PcieLaneCount[i] = pcie_width;<br>
+               }<br>
+       }<br>
+<br>
         return 0;<br>
 }<br>
 <br>
@@ -2966,6 +2975,14 @@ static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)<br>
                 }<br>
         }<br>
 <br>
+       if (data->registry_data.pcie_dpm_key_disabled) {<br>
+               PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,<br>
+                               false, data->smu_features[GNLD_DPM_LINK].smu_feature_bitmap),<br>
+               "Attempt to Disable Link DPM feature Failed!", return -EINVAL);<br>
+               data->smu_features[GNLD_DPM_LINK].enabled = false;<br>
+               data->smu_features[GNLD_DPM_LINK].supported = false;<br>
+       }<br>
+<br>
         return 0;<br>
 }<br>
 <br>
@@ -4584,6 +4601,24 @@ static int vega10_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfe<br>
         return 0;<br>
 }<br>
 <br>
+static int vega10_get_current_pcie_link_width_level(struct pp_hwmgr *hwmgr)<br>
+{<br>
+       struct amdgpu_device *adev = hwmgr->adev;<br>
+<br>
+       return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &<br>
+               PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)<br>
+               >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;<br>
+}<br>
+<br>
+static int vega10_get_current_pcie_link_speed_level(struct pp_hwmgr *hwmgr)<br>
+{<br>
+       struct amdgpu_device *adev = hwmgr->adev;<br>
+<br>
+       return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &<br>
+               PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)<br>
+               >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;<br>
+}<br>
+<br>
 static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,<br>
                 enum pp_clock_type type, char *buf)<br>
 {<br>
@@ -4592,8 +4627,9 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,<br>
         struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);<br>
         struct vega10_single_dpm_table *soc_table = &(data->dpm_table.soc_table);<br>
         struct vega10_single_dpm_table *dcef_table = &(data->dpm_table.dcef_table);<br>
-       struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table);<br>
         struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep = NULL;<br>
+       uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width;<br>
+       PPTable_t *pptable = &(data->smc_state_table.pp_table);<br>
 <br>
         int i, now, size = 0, count = 0;<br>
 <br>
@@ -4650,15 +4686,31 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,<br>
                                         "*" : "");<br>
                 break;<br>
         case PP_PCIE:<br>
-               smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentLinkIndex, &now);<br>
-<br>
-               for (i = 0; i < pcie_table->count; i++)<br>
-                       size += sprintf(buf + size, "%d: %s %s\n", i,<br>
-                                       (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s, x1" :<br>
-                                       (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s, x16" :<br>
-                                       (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s, x16" : "",<br>
-                                       (i == now) ? "*" : "");<br>
+               current_gen_speed =<br>
+                       vega10_get_current_pcie_link_speed_level(hwmgr);<br>
+               current_lane_width =<br>
+                       vega10_get_current_pcie_link_width_level(hwmgr);<br>
+               for (i = 0; i < NUM_LINK_LEVELS; i++) {<br>
+                       gen_speed = pptable->PcieGenSpeed[i];<br>
+                       lane_width = pptable->PcieLaneCount[i];<br>
+<br>
+                       size += sprintf(buf + size, "%d: %s %s %s\n", i,<br>
+                                       (gen_speed == 0) ? "2.5GT/s," :<br>
+                                       (gen_speed == 1) ? "5.0GT/s," :<br>
+                                       (gen_speed == 2) ? "8.0GT/s," :<br>
+                                       (gen_speed == 3) ? "16.0GT/s," : "",<br>
+                                       (lane_width == 1) ? "x1" :<br>
+                                       (lane_width == 2) ? "x2" :<br>
+                                       (lane_width == 3) ? "x4" :<br>
+                                       (lane_width == 4) ? "x8" :<br>
+                                       (lane_width == 5) ? "x12" :<br>
+                                       (lane_width == 6) ? "x16" : "",<br>
+                                       (current_gen_speed == gen_speed) &&<br>
+                                       (current_lane_width == lane_width) ?<br>
+                                       "*" : "");<br>
+               }<br>
                 break;<br>
+<br>
         case OD_SCLK:<br>
                 if (hwmgr->od_enabled) {<br>
                         size = sprintf(buf, "%s:\n", "OD_SCLK");<br>
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c<br>
index 196ac2a4d145..b6d7b7b224a9 100644<br>
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c<br>
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c<br>
@@ -133,6 +133,7 @@ static void vega12_set_default_registry_data(struct pp_hwmgr *hwmgr)<br>
         data->registry_data.auto_wattman_debug = 0;<br>
         data->registry_data.auto_wattman_sample_period = 100;<br>
         data->registry_data.auto_wattman_threshold = 50;<br>
+       data->registry_data.pcie_dpm_key_disabled = !(hwmgr->feature_mask & PP_PCIE_DPM_MASK);<br>
 }<br>
 <br>
 static int vega12_set_features_platform_caps(struct pp_hwmgr *hwmgr)<br>
@@ -539,6 +540,29 @@ static int vega12_override_pcie_parameters(struct pp_hwmgr *hwmgr)<br>
                 pp_table->PcieLaneCount[i] = pcie_width_arg;<br>
         }<br>
 <br>
+       /* override to the highest if it's disabled from ppfeaturmask */<br>
+       if (data->registry_data.pcie_dpm_key_disabled) {<br>
+               for (i = 0; i < NUM_LINK_LEVELS; i++) {<br>
+                       smu_pcie_arg = (i << 16) | (pcie_gen << 8) | pcie_width;<br>
+                       ret = smum_send_msg_to_smc_with_parameter(hwmgr,<br>
+                               PPSMC_MSG_OverridePcieParameters, smu_pcie_arg,<br>
+                               NULL);<br>
+                       PP_ASSERT_WITH_CODE(!ret,<br>
+                               "[OverridePcieParameters] Attempt to override pcie params failed!",<br>
+                               return ret);<br>
+<br>
+                       pp_table->PcieGenSpeed[i] = pcie_gen;<br>
+                       pp_table->PcieLaneCount[i] = pcie_width;<br>
+               }<br>
+               ret = vega12_enable_smc_features(hwmgr,<br>
+                               false,<br>
+                               data->smu_features[GNLD_DPM_LINK].smu_feature_bitmap);<br>
+               PP_ASSERT_WITH_CODE(!ret,<br>
+                               "Attempt to Disable DPM LINK Failed!",<br>
+                               return ret);<br>
+               data->smu_features[GNLD_DPM_LINK].enabled = false;<br>
+               data->smu_features[GNLD_DPM_LINK].supported = false;<br>
+       }<br>
         return 0;<br>
 }<br>
 <br>
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c<br>
index 78bbd4d666f2..213c9c6b4462 100644<br>
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c<br>
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c<br>
@@ -171,6 +171,7 @@ static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr)<br>
         data->registry_data.gfxoff_controlled_by_driver = 1;<br>
         data->gfxoff_allowed = false;<br>
         data->counter_gfxoff = 0;<br>
+       data->registry_data.pcie_dpm_key_disabled = !(hwmgr->feature_mask & PP_PCIE_DPM_MASK);<br>
 }<br>
 <br>
 static int vega20_set_features_platform_caps(struct pp_hwmgr *hwmgr)<br>
@@ -884,6 +885,30 @@ static int vega20_override_pcie_parameters(struct pp_hwmgr *hwmgr)<br>
                 pp_table->PcieLaneCount[i] = pcie_width_arg;<br>
         }<br>
 <br>
+       /* override to the highest if it's disabled from ppfeaturmask */<br>
+       if (data->registry_data.pcie_dpm_key_disabled) {<br>
+               for (i = 0; i < NUM_LINK_LEVELS; i++) {<br>
+                       smu_pcie_arg = (i << 16) | (pcie_gen << 8) | pcie_width;<br>
+                       ret = smum_send_msg_to_smc_with_parameter(hwmgr,<br>
+                               PPSMC_MSG_OverridePcieParameters, smu_pcie_arg,<br>
+                               NULL);<br>
+                       PP_ASSERT_WITH_CODE(!ret,<br>
+                               "[OverridePcieParameters] Attempt to override pcie params failed!",<br>
+                               return ret);<br>
+<br>
+                       pp_table->PcieGenSpeed[i] = pcie_gen;<br>
+                       pp_table->PcieLaneCount[i] = pcie_width;<br>
+               }<br>
+               ret = vega20_enable_smc_features(hwmgr,<br>
+                               false,<br>
+                               data->smu_features[GNLD_DPM_LINK].smu_feature_bitmap);<br>
+               PP_ASSERT_WITH_CODE(!ret,<br>
+                               "Attempt to Disable DPM LINK Failed!",<br>
+                               return ret);<br>
+               data->smu_features[GNLD_DPM_LINK].enabled = false;<br>
+               data->smu_features[GNLD_DPM_LINK].supported = false;<br>
+       }<br>
+<br>
         return 0;<br>
 }<br>
 <br>
-- <br>
2.17.1<br>
<br>
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