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[AMD Official Use Only - Internal Distribution Only]<br>
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Series is:</div>
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Reviewed-by: Alex Deucher <alexander.deucher@amd.com><br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Hawking Zhang <Hawking.Zhang@amd.com><br>
<b>Sent:</b> Thursday, March 11, 2021 10:53 PM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Zhang, Hawking <Hawking.Zhang@amd.com><br>
<b>Subject:</b> [PATCH 2/2] drm/amdgpu: support query ecc cap for SIENNA_CICHLID</font>
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<div class="PlainText">driver needs to query umc_info_v3_3 for ecc capability<br>
in sienna_cichlid<br>
<br>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com><br>
Reviewed-by: Likun Gao <Likun.Gao@amd.com><br>
---<br>
.../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 28 +++++++++++++++----<br>
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 +--<br>
2 files changed, 25 insertions(+), 7 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c<br>
index fd1d2cface2e..0612300284fb 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c<br>
@@ -117,6 +117,8 @@ union igp_info {<br>
<br>
union umc_info {<br>
struct atom_umc_info_v3_1 v31;<br>
+ struct atom_umc_info_v3_2 v32;<br>
+ struct atom_umc_info_v3_3 v33;<br>
};<br>
<br>
union vram_info {<br>
@@ -343,13 +345,29 @@ bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev)<br>
<br>
if (amdgpu_atom_parse_data_header(mode_info->atom_context,<br>
index, &size, &frev, &crev, &data_offset)) {<br>
- /* support umc_info 3.1+ */<br>
- if ((frev == 3 && crev >= 1) || (frev > 3)) {<br>
+ if (frev == 3) {<br>
umc_info = (union umc_info *)<br>
(mode_info->atom_context->bios + data_offset);<br>
- ecc_default_enabled =<br>
- (le32_to_cpu(umc_info->v31.umc_config) &<br>
- UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;<br>
+ switch (crev) {<br>
+ case 1:<br>
+ ecc_default_enabled =<br>
+ (le32_to_cpu(umc_info->v31.umc_config) &<br>
+ UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;<br>
+ break;<br>
+ case 2:<br>
+ ecc_default_enabled =<br>
+ (le32_to_cpu(umc_info->v32.umc_config) &<br>
+ UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;<br>
+ break;<br>
+ case 3:<br>
+ ecc_default_enabled =<br>
+ (le32_to_cpu(umc_info->v33.umc_config1) &<br>
+ UMC_CONFIG1__ENABLE_ECC_CAPABLE) ? true : false;<br>
+ break;<br>
+ default:<br>
+ /* unsupported crev */<br>
+ return false;<br>
+ }<br>
}<br>
}<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c<br>
index 93699ea4860c..ce025aa4e332 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c<br>
@@ -1915,11 +1915,11 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev,<br>
return;<br>
<br>
if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {<br>
- dev_info(adev->dev, "HBM ECC is active.\n");<br>
+ dev_info(adev->dev, "MEM ECC is active.\n");<br>
*hw_supported |= (1 << AMDGPU_RAS_BLOCK__UMC |<br>
1 << AMDGPU_RAS_BLOCK__DF);<br>
} else<br>
- dev_info(adev->dev, "HBM ECC is not presented.\n");<br>
+ dev_info(adev->dev, "MEM ECC is not presented.\n");<br>
<br>
if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {<br>
dev_info(adev->dev, "SRAM ECC is active.\n");<br>
-- <br>
2.17.1<br>
<br>
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