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[AMD Official Use Only - Internal Distribution Only]<br>
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<span style="font-size:12pt">Maybe add something like the following in your commit message:</span>
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<div style="font-size:12pt">"<span style="font-size:11pt;font-family:Calibri,sans-serif">The host sends this data depending on L1 policy version/asic and other scenarios. These flags ensure that there is compatibility between different guest/host/vbios versions."</span></div>
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<span style="font-size:12pt">With that added, this patch is:</span></div>
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<span style="font-size:12pt">Acked-by: Alex Deucher <alexander.deucher@amd.com></span><br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Khaire, Rohit <Rohit.Khaire@amd.com><br>
<b>Sent:</b> Tuesday, March 23, 2021 4:44 PM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>; Chang, HaiJun <HaiJun.Chang@amd.com>; Ming, Davis <Davis.Ming@amd.com>; Liu, Monk <Monk.Liu@amd.com><br>
<b>Cc:</b> Tuikov, Luben <Luben.Tuikov@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>; Xiao, Jack <Jack.Xiao@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; Xu, Feifei <Feifei.Xu@amd.com>; Wang, Kevin(Yang)
<Kevin1.Wang@amd.com>; Khaire, Rohit <Rohit.Khaire@amd.com><br>
<b>Subject:</b> [PATCH] drm/amdgpu: Add new PF2VF flags for VF register access method</font>
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<div class="PlainText">Add 3 sub flags to notify guest for indirect access of gc, mmhub and ih<br>
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Signed-off-by: Rohit Khaire <rohit.khaire@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 11 +++++++++++<br>
drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h | 17 +++++++++++++++--<br>
2 files changed, 26 insertions(+), 2 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h<br>
index 8dd624c20f89..0224f352d060 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h<br>
@@ -104,6 +104,17 @@ enum AMDGIM_FEATURE_FLAG {<br>
AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8,<br>
/* PP ONE VF MODE in GIM */<br>
AMDGIM_FEATURE_PP_ONE_VF = (1 << 4),<br>
+ /* Indirect Reg Access enabled */<br>
+ AMDGIM_FETURE_INDIRECT_REG_ACCESS = (1 << 5),<br>
+};<br>
+<br>
+enum AMDGIM_REG_ACCESS_FLAG {<br>
+ /* Use PSP to program IH_RB_CNTL */<br>
+ AMDGIM_FEATURE_IH_REG_PSP_EN = (1 << 0),<br>
+ /* Use RLC to program MMHUB regs */<br>
+ AMDGIM_FEATURE_RLC_MMHUB_EN = (1 << 1),<br>
+ /* Use RLC to program GC regs */<br>
+ AMDGIM_FEATURE_RLC_GC_EN = (1 << 2),<br>
};<br>
<br>
struct amdgim_pf2vf_info_v1 {<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h<br>
index 5355827ed0ae..7fed6377d931 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h<br>
@@ -90,11 +90,22 @@ union amd_sriov_msg_feature_flags {<br>
uint32_t host_flr_vramlost : 1;<br>
uint32_t mm_bw_management : 1;<br>
uint32_t pp_one_vf_mode : 1;<br>
- uint32_t reserved : 27;<br>
+ uint32_t reg_indirect_acc : 1;<br>
+ uint32_t reserved : 26;<br>
} flags;<br>
uint32_t all;<br>
};<br>
<br>
+union amd_sriov_reg_access_flags {<br>
+ struct {<br>
+ uint32_t vf_reg_access_ih : 1;<br>
+ uint32_t vf_reg_access_mmhub : 1;<br>
+ uint32_t vf_reg_access_gc : 1;<br>
+ uint32_t reserved : 29;<br>
+ } flags;<br>
+ uint32_t all;<br>
+};<br>
+<br>
union amd_sriov_msg_os_info {<br>
struct {<br>
uint32_t windows : 1;<br>
@@ -149,8 +160,10 @@ struct amd_sriov_msg_pf2vf_info {<br>
/* identification in ROCm SMI */<br>
uint64_t uuid;<br>
uint32_t fcn_idx;<br>
+ /* flags to indicate which register access method VF should use */<br>
+ union amd_sriov_reg_access_flags reg_access_flags;<br>
/* reserved */<br>
- uint32_t reserved[256-26];<br>
+ uint32_t reserved[256-27];<br>
};<br>
<br>
struct amd_sriov_msg_vf2pf_info_header {<br>
-- <br>
2.17.1<br>
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