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[AMD Official Use Only - Internal Distribution Only]<br>
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Shouldn't we so something similar for sdma 5.0 as well?</div>
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Alex</div>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Su, Jinzhou (Joe) <Jinzhou.Su@amd.com><br>
<b>Sent:</b> Tuesday, April 13, 2021 2:23 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Huang, Ray <Ray.Huang@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; Su, Jinzhou (Joe) <Jinzhou.Su@amd.com><br>
<b>Subject:</b> [PATCH] drm/amdgpu: Add graphics cache rinse packet for sdma</font>
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<div class="PlainText"> Add emit mem sync callback for sdma_v5_2<br>
<br>
Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 28 ++++++++++++++++++++++++++<br>
1 file changed, 28 insertions(+)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c<br>
index 93f826a7d3f0..b1ad9e52b234 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c<br>
@@ -369,6 +369,33 @@ static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring,<br>
amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));<br>
}<br>
<br>
+/**<br>
+ * sdma_v5_2_ring_emit_mem_sync - flush the IB by graphics cache rinse<br>
+ *<br>
+ * @ring: amdgpu ring pointer<br>
+ * @job: job to retrieve vmid from<br>
+ * @ib: IB object to schedule<br>
+ *<br>
+ * flush the IB by graphics cache rinse.<br>
+ */<br>
+static void sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring *ring)<br>
+{<br>
+ uint32_t gcr_cntl =<br>
+ SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |<br>
+ SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |<br>
+ SDMA_GCR_GLI_INV(1);<br>
+<br>
+ /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */<br>
+ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));<br>
+ amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));<br>
+ amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |<br>
+ SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));<br>
+ amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |<br>
+ SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));<br>
+ amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |<br>
+ SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));<br>
+}<br>
+<br>
/**<br>
* sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring<br>
*<br>
@@ -1663,6 +1690,7 @@ static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {<br>
10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */<br>
.emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */<br>
.emit_ib = sdma_v5_2_ring_emit_ib,<br>
+ .emit_mem_sync = sdma_v5_2_ring_emit_mem_sync,<br>
.emit_fence = sdma_v5_2_ring_emit_fence,<br>
.emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync,<br>
.emit_vm_flush = sdma_v5_2_ring_emit_vm_flush,<br>
-- <br>
2.27.0<br>
<br>
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