<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns:m="http://schemas.microsoft.com/office/2004/12/omml" xmlns="http://www.w3.org/TR/REC-html40"> <head> <meta http-equiv="Content-Type" content="text/html; charset=us-ascii"> <meta name="Generator" content="Microsoft Word 15 (filtered medium)"> <style></style> </head> <body lang="EN-US" link="blue" vlink="purple" style="word-wrap:break-word"> <div class="WordSection1"> <p class="msipheader87abd423" style="margin:0in"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:#317100">[AMD Public Use]</span><o:p></o:p></p> <p class="MsoNormal"><o:p> </o:p></p> <p class="MsoNormal">Updated and sent. Your review would be appreciated!<o:p></o:p></p> <p class="MsoNormal"><o:p> </o:p></p> <p class="MsoNormal">Thanks,<o:p></o:p></p> <p class="MsoNormal">Lillian<o:p></o:p></p> <p class="MsoNormal"><o:p> </o:p></p> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in"> <p class="MsoNormal"><b>From:</b> Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> <br> <b>Sent:</b> Thursday, April 15, 2021 12:27 PM<br> <b>To:</b> Zhuo, Qingqing <Qingqing.Zhuo@amd.com><br> <b>Cc:</b> amd-gfx mailing list <amd-gfx@lists.freedesktop.org>; Mark Yacoub <markyacoub@chromium.org>; Deucher, Alexander <Alexander.Deucher@amd.com>; Wheeler, Daniel <Daniel.Wheeler@amd.com>; Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>; Kazlauskas, Nicholas <Nicholas.Kazlauskas@amd.com><br> <b>Subject:</b> Re: [PATCH 1/2] drm/amd/display: Update modifier list for gfx10_3<o:p></o:p></p> </div> <p class="MsoNormal"><o:p> </o:p></p> <div> <p class="MsoNormal">Btw please add a fixes tag so it gets directed to stable releases.<o:p></o:p></p> <div> <p class="MsoNormal"><o:p> </o:p></p> </div> <div> <p class="MsoNormal">Thanks!<o:p></o:p></p> </div> </div> <p class="MsoNormal"><o:p> </o:p></p> <div> <div> <p class="MsoNormal">On Thu, Apr 15, 2021, 6:06 PM Zhuo, Qingqing <<a href="mailto:Qingqing.Zhuo@amd.com">Qingqing.Zhuo@amd.com</a>> wrote:<o:p></o:p></p> </div> <blockquote style="border:none;border-left:solid #CCCCCC 1.0pt;padding:0in 0in 0in 6.0pt;margin-left:4.8pt;margin-top:5.0pt;margin-right:0in;margin-bottom:5.0pt"> <div> <div> <p class="m1862946999310511708msipheader87abd423" style="margin:0in"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:#317100">[AMD Public Use]</span><o:p></o:p></p> <p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"> <o:p></o:p></p> <p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="color:#548235">Inline.</span><o:p></o:p></p> <p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"> <o:p></o:p></p> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in"> <p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><b>From:</b> Bas Nieuwenhuizen <<a href="mailto:bas@basnieuwenhuizen.nl" target="_blank">bas@basnieuwenhuizen.nl</a>> <br> <b>Sent:</b> Thursday, April 15, 2021 7:26 AM<br> <b>To:</b> Zhuo, Qingqing <<a href="mailto:Qingqing.Zhuo@amd.com" target="_blank">Qingqing.Zhuo@amd.com</a>><br> <b>Cc:</b> amd-gfx mailing list <<a href="mailto:amd-gfx@lists.freedesktop.org" target="_blank">amd-gfx@lists.freedesktop.org</a>>; Mark Yacoub <<a href="mailto:markyacoub@chromium.org" target="_blank">markyacoub@chromium.org</a>>; Deucher, Alexander <<a href="mailto:Alexander.Deucher@amd.com" target="_blank">Alexander.Deucher@amd.com</a>>; Wheeler, Daniel <<a href="mailto:Daniel.Wheeler@amd.com" target="_blank">Daniel.Wheeler@amd.com</a>>; Siqueira, Rodrigo <<a href="mailto:Rodrigo.Siqueira@amd.com" target="_blank">Rodrigo.Siqueira@amd.com</a>>; Kazlauskas, Nicholas <<a href="mailto:Nicholas.Kazlauskas@amd.com" target="_blank">Nicholas.Kazlauskas@amd.com</a>><br> <b>Subject:</b> Re: [PATCH 1/2] drm/amd/display: Update modifier list for gfx10_3<o:p></o:p></p> </div> <p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"> <o:p></o:p></p> <div> <div> <p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"> <o:p></o:p></p> </div> <p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"> <o:p></o:p></p> <div> <div> <p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto">On Thu, Apr 15, 2021 at 1:35 AM Qingqing Zhuo <<a href="mailto:qingqing.zhuo@amd.com" target="_blank">qingqing.zhuo@amd.com</a>> wrote:<o:p></o:p></p> </div> <blockquote style="border:none;border-left:solid #CCCCCC 1.0pt;padding:0in 0in 0in 6.0pt;margin-left:4.8pt;margin-top:5.0pt;margin-right:0in;margin-bottom:5.0pt"> <p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto">[Why]<br> Current list only includes modifiers where DCC_MAX_COMPRESSED_BLOCK<br> is set to AMD_FMT_MOD_DCC_BLOCK_128B, while AMD_FMT_MOD_DCC_BLOCK_64B<br> is also supported and used by userspace.<br> <br> [How]<br> Add AMD_FMT_MOD_DCC_BLOCK_64B to modifiers with DCC supported.<br> <br> Signed-off-by: Qingqing Zhuo <<a href="mailto:qingqing.zhuo@amd.com" target="_blank">qingqing.zhuo@amd.com</a>><br> ---<br> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 23 +++++++++++++++++++<br> 1 file changed, 23 insertions(+)<br> <br> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c<br> index e29cb2e956db..c3cbc3d298e7 100644<br> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c<br> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c<br> @@ -4535,6 +4535,17 @@ add_gfx10_3_modifiers(const struct amdgpu_device *adev,<br> int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);<br> int pkrs = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs);<br> <br> + add_modifier(mods, size, capacity, AMD_FMT_MOD |<br> + AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |<br> + AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |<br> + AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |<br> + AMD_FMT_MOD_SET(PACKERS, pkrs) |<br> + AMD_FMT_MOD_SET(DCC, 1) |<br> + AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |<br> + AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |<br> + AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |<br> + AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));<o:p></o:p></p> </blockquote> <div> <p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"> <o:p></o:p></p> </div> <div> <p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto">Thanks for finding this issue. Looking at it it looks to me like the original entries are mistaken. Can we just change the DCC_MAX_COMPRESSED_BLOCK in the already existing DCC entries? Looks like Mesa always uses the AMD_FMT_MOD_DCC_BLOCK_64B anyway, and I don't think DCC_INDEPENDENT_64B=1 + DCC_MAX_COMPRESSED_BLOCK=AMD_FMT_MOD_DCC_BLOCK_128B makes sense.<o:p></o:p></p> </div> <div> <p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"> <o:p></o:p></p> <p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="color:#548235">Thanks for the suggestion. Will send out an updated version soon.</span><o:p></o:p></p> <p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="color:#548235"> </span><o:p></o:p></p> </div> <blockquote style="border:none;border-left:solid #CCCCCC 1.0pt;padding:0in 0in 0in 6.0pt;margin-left:4.8pt;margin-top:5.0pt;margin-right:0in;margin-bottom:5.0pt"> <p class="MsoNormal" style="mso-margin-top-alt:auto;margin-bottom:12.0pt">+<br> add_modifier(mods, size, capacity, AMD_FMT_MOD |<br> AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |<br> AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |<br> @@ -4546,6 +4557,18 @@ add_gfx10_3_modifiers(const struct amdgpu_device *adev,<br> AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |<br> AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B));<br> <br> + add_modifier(mods, size, capacity, AMD_FMT_MOD |<br> + AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |<br> + AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |<br> + AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |<br> + AMD_FMT_MOD_SET(PACKERS, pkrs) |<br> + AMD_FMT_MOD_SET(DCC, 1) |<br> + AMD_FMT_MOD_SET(DCC_RETILE, 1) |<br> + AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |<br> + AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |<br> + AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |<br> + AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));<br> +<br> add_modifier(mods, size, capacity, AMD_FMT_MOD |<br> AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |<br> AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |<br> -- <br> 2.17.1<o:p></o:p></p> </blockquote> </div> </div> </div> </div> </blockquote> </div> </div> </body> </html>