<div dir="ltr"><div dir="ltr"><br></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Thu, Apr 15, 2021 at 1:35 AM Qingqing Zhuo <<a href="mailto:qingqing.zhuo@amd.com">qingqing.zhuo@amd.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">[Why]<br>
Current list only includes modifiers where DCC_MAX_COMPRESSED_BLOCK<br>
is set to AMD_FMT_MOD_DCC_BLOCK_128B, while AMD_FMT_MOD_DCC_BLOCK_64B<br>
is also supported and used by userspace.<br>
<br>
[How]<br>
Add AMD_FMT_MOD_DCC_BLOCK_64B to modifiers with DCC supported.<br>
<br>
Signed-off-by: Qingqing Zhuo <<a href="mailto:qingqing.zhuo@amd.com" target="_blank">qingqing.zhuo@amd.com</a>><br>
---<br>
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 23 +++++++++++++++++++<br>
1 file changed, 23 insertions(+)<br>
<br>
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c<br>
index e29cb2e956db..c3cbc3d298e7 100644<br>
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c<br>
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c<br>
@@ -4535,6 +4535,17 @@ add_gfx10_3_modifiers(const struct amdgpu_device *adev,<br>
int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);<br>
int pkrs = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs);<br>
<br>
+ add_modifier(mods, size, capacity, AMD_FMT_MOD |<br>
+ AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |<br>
+ AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |<br>
+ AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |<br>
+ AMD_FMT_MOD_SET(PACKERS, pkrs) |<br>
+ AMD_FMT_MOD_SET(DCC, 1) |<br>
+ AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |<br>
+ AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |<br>
+ AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |<br>
+ AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));<br></blockquote><div><br></div><div>Thanks for finding this issue. Looking at it it looks to me like the original entries are mistaken. Can we just change the DCC_MAX_COMPRESSED_BLOCK in the already existing DCC entries? Looks like Mesa always uses the AMD_FMT_MOD_DCC_BLOCK_64B anyway, and I don't think DCC_INDEPENDENT_64B=1 + DCC_MAX_COMPRESSED_BLOCK=AMD_FMT_MOD_DCC_BLOCK_128B makes sense.</div><div><br></div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
+<br>
add_modifier(mods, size, capacity, AMD_FMT_MOD |<br>
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |<br>
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |<br>
@@ -4546,6 +4557,18 @@ add_gfx10_3_modifiers(const struct amdgpu_device *adev,<br>
AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |<br>
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B));<br>
<br>
+ add_modifier(mods, size, capacity, AMD_FMT_MOD |<br>
+ AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |<br>
+ AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |<br>
+ AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |<br>
+ AMD_FMT_MOD_SET(PACKERS, pkrs) |<br>
+ AMD_FMT_MOD_SET(DCC, 1) |<br>
+ AMD_FMT_MOD_SET(DCC_RETILE, 1) |<br>
+ AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |<br>
+ AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |<br>
+ AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |<br>
+ AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));<br>
+<br>
add_modifier(mods, size, capacity, AMD_FMT_MOD |<br>
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |<br>
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |<br>
-- <br>
2.17.1<br>
<br>
</blockquote></div></div>