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[AMD Official Use Only - Internal Distribution Only]<br>
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<span style="color:black;font-size:12pt;font-family:Calibri,sans-serif;background-color:white">Reviewed-by: Tao Zhou <<a href="mailto:tao.zhou1@amd.com" target="_blank" rel="noopener noreferrer" data-auth="NotApplicable" data-linkindex="0">tao.zhou1@amd.com</a>></span><br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Jiansong Chen <Jiansong.Chen@amd.com><br>
<b>Sent:</b> Monday, April 19, 2021 4:47 PM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Zhou1, Tao <Tao.Zhou1@amd.com>; Gui, Jack <Jack.Gui@amd.com>; Chen, Jiansong (Simon) <Jiansong.Chen@amd.com><br>
<b>Subject:</b> [PATCH] drm/amdgpu: fix GCR_GENERAL_CNTL offset for dimgrey_cavefish</font>
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<div class="PlainText">dimgrey_cavefish has similar gc_10_3 ip with sienna_cichlid,<br>
so follow its registers offset setting.<br>
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Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com><br>
Change-Id: I2c8f1022c0b4c5baf70d09ec99b7b2ca8da36bba<br>
---<br>
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-<br>
1 file changed, 1 insertion(+), 1 deletion(-)<br>
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diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c<br>
index 85a6a10e048f..49fd10a15707 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c<br>
@@ -3377,7 +3377,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =<br>
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),<br>
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),<br>
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),<br>
- SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00001d00, 0x00000500),<br>
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),<br>
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),<br>
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),<br>
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),<br>
-- <br>
2.25.1<br>
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