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Hi Horace,<br>
<br>
that is correct, but also completely irrelevant.<br>
<br>
What we do here is to wait for the TLB flush to avoid starting
operations with invalid cache data.<br>
<br>
But a parallel FLR clears the cache anyway and also prevents any new
operation from starting, so it is perfectly valid to timeout and
just continue with an error message.<br>
<br>
<br>
On the other hand waiting for 6 seconds in a busy loop will most
likely trigger the watchdog timer and potentially kill our process.<br>
<br>
That is a rather clear no-go, we simply can't increase timeouts
infinitely.<br>
<br>
Regards,<br>
Christian.<br>
<br>
<div class="moz-cite-prefix">Am 19.05.21 um 16:39 schrieb Chen,
Horace:<br>
</div>
<blockquote type="cite" cite="mid:DM4PR12MB507287194C10E15669DEBAEDE12B9@DM4PR12MB5072.namprd12.prod.outlook.com">
<style type="text/css" style="display:none;">P {margin-top:0;margin-bottom:0;}</style>
<p style="font-family:Arial;font-size:10pt;color:#0000FF;margin:15pt;" align="Left">
[AMD Official Use Only]<br>
</p>
<br>
<div>
<div style="font-family: Calibri, Arial, Helvetica, sans-serif;
font-size: 12pt; color: rgb(0, 0, 0);">
Hi Christian,</div>
<div style="font-family: Calibri, Arial, Helvetica, sans-serif;
font-size: 12pt; color: rgb(0, 0, 0);">
<br>
</div>
<div style="font-family: Calibri, Arial, Helvetica, sans-serif;
font-size: 12pt; color: rgb(0, 0, 0);">
I think the problem is that a non-FLRed VF will not know that
another VF got an FLR, unless host triggered a whole GPU
reset.
<br>
</div>
<div style="font-family: Calibri, Arial, Helvetica, sans-serif;
font-size: 12pt; color: rgb(0, 0, 0);">
So in the worst situation, for example the VF0 to VF10 are all
hang and will be FLRed one by one, the VF11 will not know that
there are FLRs happened, in VF11's prespective, it just see
the fence didn't come back for about 5.5(0.5*11) seconds.</div>
<div style="font-family: Calibri, Arial, Helvetica, sans-serif;
font-size: 12pt; color: rgb(0, 0, 0);">
<br>
</div>
<div style="font-family: Calibri, Arial, Helvetica, sans-serif;
font-size: 12pt; color: rgb(0, 0, 0);">
Thanks & Regards,</div>
<div style="font-family: Calibri, Arial, Helvetica, sans-serif;
font-size: 12pt; color: rgb(0, 0, 0);">
Horace.<br>
</div>
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<div id="appendonsend"><br>
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<hr tabindex="-1" style="display:inline-block; width:98%">
<div id="divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" face="Calibri, sans-serif" color="#000000"><b>发件人:</b>
Koenig, Christian <a class="moz-txt-link-rfc2396E" href="mailto:Christian.Koenig@amd.com"><Christian.Koenig@amd.com></a><br>
<b>发送时间:</b> 2021年5月19日 19:49<br>
<b>收件人:</b> Liu, Cheng Zhe <a class="moz-txt-link-rfc2396E" href="mailto:ChengZhe.Liu@amd.com"><ChengZhe.Liu@amd.com></a>;
Christian König <a class="moz-txt-link-rfc2396E" href="mailto:ckoenig.leichtzumerken@gmail.com"><ckoenig.leichtzumerken@gmail.com></a>;
<a class="moz-txt-link-abbreviated" href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a>
<a class="moz-txt-link-rfc2396E" href="mailto:amd-gfx@lists.freedesktop.org"><amd-gfx@lists.freedesktop.org></a><br>
<b>抄送:</b> Xiao, Jack <a class="moz-txt-link-rfc2396E" href="mailto:Jack.Xiao@amd.com"><Jack.Xiao@amd.com></a>; Xu,
Feifei <a class="moz-txt-link-rfc2396E" href="mailto:Feifei.Xu@amd.com"><Feifei.Xu@amd.com></a>; Wang, Kevin(Yang)
<a class="moz-txt-link-rfc2396E" href="mailto:Kevin1.Wang@amd.com"><Kevin1.Wang@amd.com></a>; Tuikov, Luben
<a class="moz-txt-link-rfc2396E" href="mailto:Luben.Tuikov@amd.com"><Luben.Tuikov@amd.com></a>; Deucher, Alexander
<a class="moz-txt-link-rfc2396E" href="mailto:Alexander.Deucher@amd.com"><Alexander.Deucher@amd.com></a>; Zhang, Hawking
<a class="moz-txt-link-rfc2396E" href="mailto:Hawking.Zhang@amd.com"><Hawking.Zhang@amd.com></a>; Chen, Horace
<a class="moz-txt-link-rfc2396E" href="mailto:Horace.Chen@amd.com"><Horace.Chen@amd.com></a><br>
<b>主题:</b> Re: [PATCH] drm/amdgpu: Increase tlb flush
timeout for sriov</font>
<div> </div>
</div>
<div class="BodyFragment"><font size="2"><span style="font-size:11pt">
<div class="PlainText">Yeah, but you can't do that it
will probably trigger the watchdog timer.<br>
<br>
The usec_timeout is named this way because it is a
usec timeout. <br>
Anything large than 1ms is a no-go here.<br>
<br>
When the other instances do a FLR we don't really need
to wait for the <br>
TLB flush anyway since any FLR will kill that.<br>
<br>
Christian.<br>
<br>
Am 19.05.21 um 13:08 schrieb Liu, Cheng Zhe:<br>
> [AMD Official Use Only]<br>
><br>
> We support 12 VF at most. In worst case, the
first 11 all IDLE fail and do FLR, it will need 11 *
500ms to switch to the 12nd VF,<br>
> so I set 12 * 500ms for the timeout.<br>
><br>
> -----Original Message-----<br>
> From: Christian König
<a class="moz-txt-link-rfc2396E" href="mailto:ckoenig.leichtzumerken@gmail.com"><ckoenig.leichtzumerken@gmail.com></a><br>
> Sent: Wednesday, May 19, 2021 6:08 PM<br>
> To: Liu, Cheng Zhe <a class="moz-txt-link-rfc2396E" href="mailto:ChengZhe.Liu@amd.com"><ChengZhe.Liu@amd.com></a>;
<a class="moz-txt-link-abbreviated" href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a><br>
> Cc: Xiao, Jack <a class="moz-txt-link-rfc2396E" href="mailto:Jack.Xiao@amd.com"><Jack.Xiao@amd.com></a>; Xu,
Feifei <a class="moz-txt-link-rfc2396E" href="mailto:Feifei.Xu@amd.com"><Feifei.Xu@amd.com></a>; Wang, Kevin(Yang)
<a class="moz-txt-link-rfc2396E" href="mailto:Kevin1.Wang@amd.com"><Kevin1.Wang@amd.com></a>; Tuikov, Luben
<a class="moz-txt-link-rfc2396E" href="mailto:Luben.Tuikov@amd.com"><Luben.Tuikov@amd.com></a>; Deucher, Alexander
<a class="moz-txt-link-rfc2396E" href="mailto:Alexander.Deucher@amd.com"><Alexander.Deucher@amd.com></a>; Koenig, Christian
<a class="moz-txt-link-rfc2396E" href="mailto:Christian.Koenig@amd.com"><Christian.Koenig@amd.com></a>; Zhang, Hawking
<a class="moz-txt-link-rfc2396E" href="mailto:Hawking.Zhang@amd.com"><Hawking.Zhang@amd.com></a><br>
> Subject: Re: [PATCH] drm/amdgpu: Increase tlb
flush timeout for sriov<br>
><br>
> Am 19.05.21 um 11:32 schrieb Chengzhe Liu:<br>
>> When there is 12 VF, we need to increase the
timeout<br>
> NAK, 6 seconds is way to long to wait polling on
a fence.<br>
><br>
> Why should an invalidation take that long? The
engine are per VF just to avoid exactly that problem.<br>
><br>
> Christian.<br>
><br>
>> Signed-off-by: Chengzhe Liu
<a class="moz-txt-link-rfc2396E" href="mailto:ChengZhe.Liu@amd.com"><ChengZhe.Liu@amd.com></a><br>
>> ---<br>
>> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 6
+++++-<br>
>> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 6
+++++-<br>
>> 2 files changed, 10 insertions(+), 2
deletions(-)<br>
>><br>
>> diff --git
a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c<br>
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c<br>
>> index f02dc904e4cf..a5f005c5d0ec 100644<br>
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c<br>
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c<br>
>> @@ -404,6 +404,7 @@ static int
gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device
*adev,<br>
>> uint32_t seq;<br>
>> uint16_t queried_pasid;<br>
>> bool ret;<br>
>> + uint32_t sriov_usec_timeout = 6000000;
/* wait for 12 * 500ms for<br>
>> +SRIOV */<br>
>> struct amdgpu_ring *ring =
&adev->gfx.kiq.ring;<br>
>> struct amdgpu_kiq *kiq =
&adev->gfx.kiq;<br>
>> <br>
>> @@ -422,7 +423,10 @@ static int
gmc_v10_0_flush_gpu_tlb_pasid(struct<br>
>> amdgpu_device *adev,<br>
>> <br>
>> amdgpu_ring_commit(ring);<br>
>>
spin_unlock(&adev->gfx.kiq.ring_lock);<br>
>> - r =
amdgpu_fence_wait_polling(ring, seq,
adev->usec_timeout);<br>
>> + if (amdgpu_sriov_vf(adev))<br>
>> + r =
amdgpu_fence_wait_polling(ring, seq,
sriov_usec_timeout);<br>
>> + else<br>
>> + r =
amdgpu_fence_wait_polling(ring, seq,
adev->usec_timeout);<br>
>> if (r < 1) {<br>
>> dev_err(adev->dev,
"wait for kiq fence error: %ld.\n", r);<br>
>> return -ETIME;<br>
>> diff --git
a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c<br>
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c<br>
>> index ceb3968d8326..e4a18d8f75c2 100644<br>
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c<br>
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c<br>
>> @@ -857,6 +857,7 @@ static int
gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device
*adev,<br>
>> uint32_t seq;<br>
>> uint16_t queried_pasid;<br>
>> bool ret;<br>
>> + uint32_t sriov_usec_timeout = 6000000;
/* wait for 12 * 500ms for<br>
>> +SRIOV */<br>
>> struct amdgpu_ring *ring =
&adev->gfx.kiq.ring;<br>
>> struct amdgpu_kiq *kiq =
&adev->gfx.kiq;<br>
>> <br>
>> @@ -896,7 +897,10 @@ static int
gmc_v9_0_flush_gpu_tlb_pasid(struct<br>
>> amdgpu_device *adev,<br>
>> <br>
>> amdgpu_ring_commit(ring);<br>
>>
spin_unlock(&adev->gfx.kiq.ring_lock);<br>
>> - r =
amdgpu_fence_wait_polling(ring, seq,
adev->usec_timeout);<br>
>> + if (amdgpu_sriov_vf(adev))<br>
>> + r =
amdgpu_fence_wait_polling(ring, seq,
sriov_usec_timeout);<br>
>> + else<br>
>> + r =
amdgpu_fence_wait_polling(ring, seq,
adev->usec_timeout);<br>
>> if (r < 1) {<br>
>> dev_err(adev->dev,
"wait for kiq fence error: %ld.\n", r);<br>
>>
up_read(&adev->reset_sem);<br>
<br>
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