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[Public]<br>
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I think both of those candidates have drawbacks
<div>** option #1 has a clash with the limit_level</div>
<div> eg.</div>
<div> enum pp_power_limit_level limit_level;</div>
<div> enum pp_power_limit power_limit;</div>
<div> </div>
<div> power_limit = PP_PWR_LIMIT_DEFAULT; // name clash</div>
<div><br>
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<div>** option #2 doesn't describe the usage, and might as well just be a uint</div>
<div> power_limit = PP_PWR_LIMIT_0; // no use in reading code later</div>
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<div>Would you accept "category" as a suitable solution?</div>
<div> eg.</div>
<div> enum pp_power_category</div>
<div> {</div>
<div>                PP_PWR_CATEGORY_DEFAULT,</div>
<div>                PP_PWR_CATEGORY_FAST,</div>
<div>                PP_PWR_CATEGORY_APU,</div>
<div>                PP_PWR_CATEGORY_PLATFORM,</div>
<div> };</div>
<div><br>
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<div>Other possibilities may be</div>
<div>** class</div>
<div>** subsystem</div>
<div>** type</div>
<div>** element</div>
<div><br>
</div>
<div>Thanks</div>
<span>Darren</span><br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Lazar, Lijo <Lijo.Lazar@amd.com><br>
<b>Sent:</b> Wednesday, June 2, 2021 12:32 AM<br>
<b>To:</b> Powell, Darren <Darren.Powell@amd.com>; amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Subject:</b> RE: [PATCH 2/6] amdgpu/pm: clean up smu_get_power_limit function signature</font>
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<p class="x_msipheaderc10f11a2" style="margin:0in"><span style="font-size:10.0pt; font-family:"Arial",sans-serif; color:green">[Public]</span></p>
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<p class="x_MsoNormal">I’m looking for an appropriate name that can accommodate more limits like
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<p class="x_MsoNormal">enum pp_power_limit</p>
<p class="x_MsoNormal">{</p>
<p class="x_MsoNormal">                PP_PWR_LIMIT_DEFAULT,</p>
<p class="x_MsoNormal">                PP_PWR_LIMIT_FAST, </p>
<p class="x_MsoNormal" style="text-indent:.5in">PP_PWR_LIMIT_APU,</p>
<p class="x_MsoNormal">                PP_PWR_LIMIT_PLATFORM,</p>
<p class="x_MsoNormal">};</p>
<p class="x_MsoNormal"> </p>
<p class="x_MsoNormal">Or simply different limits where the meaning may change based on ASIC - LIMIT2 could be platform power limit for ASIC1 or LIMIT2 could be max power allocation for a domain (say memory) for ASIC2</p>
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<p class="x_MsoNormal">enum pp_power_limit</p>
<p class="x_MsoNormal">{</p>
<p class="x_MsoNormal">                PP_PWR_LIMIT_0,</p>
<p class="x_MsoNormal">                PP_PWR_LIMIT_1,</p>
<p class="x_MsoNormal">                PP_PWR_LIMIT_2,</p>
<p class="x_MsoNormal">                PP_PWR_LIMIT_3,</p>
<p class="x_MsoNormal">};</p>
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<p class="x_MsoNormal">Thanks,</p>
<p class="x_MsoNormal">Lijo</p>
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<p class="x_MsoNormal"><b>From:</b> Powell, Darren <Darren.Powell@amd.com> <br>
<b>Sent:</b> Wednesday, June 2, 2021 9:25 AM<br>
<b>To:</b> Lazar, Lijo <Lijo.Lazar@amd.com>; amd-gfx@lists.freedesktop.org<br>
<b>Subject:</b> Re: [PATCH 2/6] amdgpu/pm: clean up smu_get_power_limit function signature</p>
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<p style="margin:15.0pt"><span style="font-size:10.0pt; font-family:"Arial",sans-serif; color:green">[Public]</span></p>
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<p class="x_MsoNormal"><span style="font-size:12.0pt; color:black">I'm not sure exactly what you are looking for. The enums sample_window and limit_level map to power{1,2} and cap{min,max,default,current} respectively. I added the enums to make the function
 signatures more readable and stop the use of value as an input and output variable.</span></p>
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<p class="x_MsoNormal"><span style="font-size:12.0pt; color:black">Please give more specific example?</span></p>
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<p class="x_MsoNormal"><span style="font-size:12.0pt; color:black">Darren </span></p>
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<p class="x_MsoNormal"><span style="font-size:12.0pt; color:black">= HWMON Mapping =</span></p>
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<p class="x_MsoNormal"><span style="font-size:12.0pt; color:black">== Read ==</span></p>
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<pre style="line-height:15.6pt; background:#F8F9FA"><span style="font-size:10.5pt; color:black">SENSOR(power1_average)     amdgpu_hwmon_show_power_avg(0)           amdgpu_dpm_read_sensor(AMDGPU_PP_SENSOR_GPU_POWER)</span></pre>
<pre style="line-height:15.6pt; background:#F8F9FA"><span style="font-size:10.5pt; color:black">SENSOR(power1_cap_max)     amdgpu_hwmon_show_power_cap_max(0)       get_power_limit(PP_PWR_LIMIT_MAX, PP_PWR_WINDOW_DEFAULT)</span></pre>
<pre style="line-height:15.6pt; background:#F8F9FA"><span style="font-size:10.5pt; color:black">SENSOR(power1_cap_min)     amdgpu_hwmon_show_power_cap_min(0)       0</span></pre>
<pre style="line-height:15.6pt; background:#F8F9FA"><span style="font-size:10.5pt; color:black">SENSOR(power1_cap)         amdgpu_hwmon_show_power_cap(0)           get_power_limit(PP_PWR_LIMIT_CURRENT, PP_PWR_WINDOW_DEFAULT)</span></pre>
<pre style="line-height:15.6pt; background:#F8F9FA"><span style="font-size:10.5pt; color:black">SENSOR(power1_cap_default) amdgpu_hwmon_show_power_cap_default(0)   get_power_limit(PP_PWR_LIMIT_DEFAULT, PP_PWR_WINDOW_DEFAULT)</span></pre>
<pre style="line-height:15.6pt; background:#F8F9FA"><span style="font-size:10.5pt; color:black">SENSOR(power1_label)       amdgpu_hwmon_show_power_label(0)         "slowPPT"</span></pre>
<pre style="line-height:15.6pt; background:#F8F9FA"><span style="font-size:10.5pt; color:black">SENSOR(power2_average)     amdgpu_hwmon_show_power_avg(1)           amdgpu_dpm_read_sensor(AMDGPU_PP_SENSOR_GPU_POWER)</span></pre>
<pre style="line-height:15.6pt; background:#F8F9FA"><span style="font-size:10.5pt; color:black">SENSOR(power2_cap_max)     amdgpu_hwmon_show_power_cap_max(1)       get_power_limit(PP_PWR_LIMIT_MAX, PP_PWR_WINDOW_FAST)</span></pre>
<pre style="line-height:15.6pt; background:#F8F9FA"><span style="font-size:10.5pt; color:black">SENSOR(power2_cap_min)     amdgpu_hwmon_show_power_cap_min(1)       0</span></pre>
<pre style="line-height:15.6pt; background:#F8F9FA"><span style="font-size:10.5pt; color:black">SENSOR(power2_cap)         amdgpu_hwmon_show_power_cap(1)           get_power_limit(PP_PWR_LIMIT_CURRENT, PP_PWR_WINDOW_FAST)</span></pre>
<pre style="line-height:15.6pt; background:#F8F9FA"><span style="font-size:10.5pt; color:black">SENSOR(power2_cap_default) amdgpu_hwmon_show_power_cap_default(1)   get_power_limit(PP_PWR_LIMIT_DEFAULT, PP_PWR_WINDOW_FAST)</span></pre>
<pre style="line-height:15.6pt; background:#F8F9FA"><span style="font-size:10.5pt; color:black">SENSOR(power2_label)       amdgpu_hwmon_show_power_label(1)         "fastPPT"</span></pre>
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<p class="x_MsoNormal"><span style="font-size:12.0pt; color:black">== Write ==</span></p>
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<pre style="line-height:15.6pt; background:#F8F9FA"><span style="font-size:10.5pt; color:black">SENSOR(power1_cap)         amdgpu_hwmon_set_power_cap(0,value)      set_power_limit( (0<<24) || value )</span></pre>
<pre style="line-height:15.6pt; background:#F8F9FA"><span style="font-size:10.5pt; color:black">SENSOR(power2_cap)         amdgpu_hwmon_set_power_cap(1,value)      set_power_limit( (1<<24) || value )</span></pre>
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<p class="x_MsoNormal"><span style="font-size:12.0pt; color:black">= Summary =</span></p>
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<pre style="line-height:15.6pt; background:#F8F9FA"><span style="font-size:10.5pt; color:black">power1 => PP_PWR_WINDOW_DEFAULT   ( label ("slowPPT"))</span></pre>
<pre style="line-height:15.6pt; background:#F8F9FA"><span style="font-size:10.5pt; color:black">power2 => PP_PWR_WINDOW_FAST      ( label ("fastPPT"))</span></pre>
<pre style="line-height:15.6pt; background:#F8F9FA"><span style="font-size:10.5pt; color:black">power_avg         => AMDGPU_PP_SENSOR_GPU_POWER</span></pre>
<pre style="line-height:15.6pt; background:#F8F9FA"><span style="font-size:10.5pt; color:black">power_cap_max     => PP_PWR_LIMIT_MAX</span></pre>
<pre style="line-height:15.6pt; background:#F8F9FA"><span style="font-size:10.5pt; color:black">power_cap_min     => PP_PWR_LIMIT_MIN (optimized to 0)</span></pre>
<pre style="line-height:15.6pt; background:#F8F9FA"><span style="font-size:10.5pt; color:black">power_cap         => PP_PWR_LIMIT_CURRENT</span></pre>
<pre style="line-height:15.6pt; background:#F8F9FA"><span style="font-size:10.5pt; color:black">power_cap_default => PP_PWR_LIMIT_DEFAULT</span></pre>
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<p class="x_MsoNormal"><b><span style="color:black">From:</span></b><span style="color:black"> Lazar, Lijo <<a href="mailto:Lijo.Lazar@amd.com">Lijo.Lazar@amd.com</a>><br>
<b>Sent:</b> Tuesday, June 1, 2021 12:56 AM<br>
<b>To:</b> Powell, Darren <<a href="mailto:Darren.Powell@amd.com">Darren.Powell@amd.com</a>>;
<a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a> <<a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a>><br>
<b>Subject:</b> RE: [PATCH 2/6] amdgpu/pm: clean up smu_get_power_limit function signature</span>
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<p class="x_xmsipheaderc10f11a2" style="margin:0in"><span style="font-size:10.0pt; font-family:"Arial",sans-serif; color:green">[Public]</span></p>
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<p class="x_xmsonormal">May be just call it power_limit or power_cap similar to hwmon. The various limits correspond to hwmon power[1-*]_cap and levels correspond to min/ max etc.</p>
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<p class="x_xmsonormal">Thanks,</p>
<p class="x_xmsonormal">Lijo</p>
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<p class="x_xmsonormal"><b>From:</b> Powell, Darren <<a href="mailto:Darren.Powell@amd.com">Darren.Powell@amd.com</a>>
<br>
<b>Sent:</b> Tuesday, June 1, 2021 4:50 AM<br>
<b>To:</b> Lazar, Lijo <<a href="mailto:Lijo.Lazar@amd.com">Lijo.Lazar@amd.com</a>>;
<a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a><br>
<b>Subject:</b> Re: [PATCH 2/6] amdgpu/pm: clean up smu_get_power_limit function signature</p>
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<p style="margin:15.0pt"><span style="font-size:10.0pt; font-family:"Arial",sans-serif; color:green">[Public]</span></p>
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<p class="x_xmsonormal"><span style="font-family:"Segoe UI",sans-serif; color:black"><br>
<span style="background:white">>< > The limits are not limited to sample window. There are limits like APU only limit, platform limit and totally obscure ones like PPT0/PPT1 etc.</span><br>
<span style="background:white">>It's better that the new enum takes care of those as well in case there is a need to make them available through sysfs.</span></span></p>
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<p class="x_xmsonormal"><span style="font-size:12.0pt; color:black">I think you mean something more like this?</span></p>
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<p class="x_xmsonormal"><span style="font-family:"Segoe UI",sans-serif; color:black; background:white">+ enum pp_power_constraints</span><span style="font-size:12.0pt; color:black"><br>
</span><span style="font-family:"Segoe UI",sans-serif; color:black; background:white">+{</span><span style="font-family:"Segoe UI",sans-serif; color:black"><br>
<span style="background:white">+       PP_PWR_CONSTRAINT_DEFAULT,</span><br>
<span style="background:white">+       PP_PWR_CONSTRAINT_FASTWINDOW,</span><br>
<span style="background:white">+};</span><br>
<span style="background:white">+</span></span></p>
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<p class="x_xmsonormal"><b><span style="color:black">From:</span></b><span style="color:black"> Lazar, Lijo <<a href="mailto:Lijo.Lazar@amd.com">Lijo.Lazar@amd.com</a>><br>
<b>Sent:</b> Monday, May 31, 2021 2:04 AM<br>
<b>To:</b> Powell, Darren <<a href="mailto:Darren.Powell@amd.com">Darren.Powell@amd.com</a>>;
<a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a> <<a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a>><br>
<b>Subject:</b> RE: [PATCH 2/6] amdgpu/pm: clean up smu_get_power_limit function signature</span>
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<p class="x_xmsonormal">[Public]<br>
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-----Original Message-----<br>
From: Powell, Darren <<a href="mailto:Darren.Powell@amd.com">Darren.Powell@amd.com</a>>
<br>
Sent: Saturday, May 29, 2021 4:36 AM<br>
To: <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a><br>
Cc: Powell, Darren <<a href="mailto:Darren.Powell@amd.com">Darren.Powell@amd.com</a>><br>
Subject: [PATCH 2/6] amdgpu/pm: clean up smu_get_power_limit function signature<br>
<br>
 add two new powerplay enums (limit_level, sample_window)  add enums to smu_get_power_limit signature  remove input bitfield stuffing of output variable limit  update calls to smu_get_power_limit<br>
<br>
* Test<br>
 AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1`  AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | cut -d " " -f 10`  HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON}<br>
<br>
 lspci -nn | grep "VGA\|Display" ; \<br>
 echo "=== power1 cap ===" ; cat $HWMON_DIR/power1_cap ;           \<br>
 echo "=== power1 cap max ===" ; cat $HWMON_DIR/power1_cap_max ;   \<br>
 echo "=== power1 cap def ===" ; cat $HWMON_DIR/power1_cap_default<br>
<br>
Signed-off-by: Darren Powell <<a href="mailto:darren.powell@amd.com">darren.powell@amd.com</a>><br>
---<br>
 .../gpu/drm/amd/include/kgd_pp_interface.h    | 14 ++++++++<br>
 drivers/gpu/drm/amd/pm/amdgpu_pm.c            | 18 +++++-----<br>
 drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h       |  3 +-<br>
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c     | 34 +++++++++++++++++--<br>
 4 files changed, 57 insertions(+), 12 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h<br>
index b1cd52a9d684..ddbf802ea8ad 100644<br>
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h<br>
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h<br>
@@ -192,6 +192,20 @@ enum pp_df_cstate {<br>
         DF_CSTATE_ALLOW,<br>
 };<br>
 <br>
+enum pp_power_limit_level<br>
+{<br>
+       PP_PWR_LIMIT_MIN = -1,<br>
+       PP_PWR_LIMIT_CURRENT,<br>
+       PP_PWR_LIMIT_DEFAULT,<br>
+       PP_PWR_LIMIT_MAX,<br>
+};<br>
+<br>
+ enum pp_power_sample_window<br>
+{<br>
+       PP_PWR_WINDOW_DEFAULT,<br>
+       PP_PWR_WINDOW_FAST,<br>
+};<br>
+<br>
<br>
< > The limits are not limited to sample window. There are limits like APU only limit, platform limit and totally obscure ones like PPT0/PPT1 etc.
<br>
It's better that the new enum takes care of those as well in case there is a need to make them available through sysfs.<br>
<br>
Thanks,<br>
Lijo<br>
<br>
 #define PP_GROUP_MASK        0xF0000000<br>
 #define PP_GROUP_SHIFT       28<br>
 <br>
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c<br>
index 13da377888d2..f7b45803431d 100644<br>
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c<br>
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c<br>
@@ -2717,8 +2717,8 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,  {<br>
         struct amdgpu_device *adev = dev_get_drvdata(dev);<br>
         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;<br>
-       int limit_type = to_sensor_dev_attr(attr)->index;<br>
-       uint32_t limit = limit_type << 24;<br>
+       enum pp_power_sample_window sample_window = to_sensor_dev_attr(attr)->index;<br>
+       uint32_t limit;<br>
         uint32_t max_limit = 0;<br>
         ssize_t size;<br>
         int r;<br>
@@ -2735,7 +2735,7 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,<br>
         }<br>
 <br>
         if (is_support_sw_smu(adev)) {<br>
-               smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_MAX);<br>
+               smu_get_power_limit(&adev->smu, &limit, PP_PWR_LIMIT_MAX, <br>
+sample_window);<br>
                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);<br>
         } else if (pp_funcs && pp_funcs->get_power_limit) {<br>
                 pp_funcs->get_power_limit(adev->powerplay.pp_handle,<br>
@@ -2757,8 +2757,8 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,  {<br>
         struct amdgpu_device *adev = dev_get_drvdata(dev);<br>
         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;<br>
-       int limit_type = to_sensor_dev_attr(attr)->index;<br>
-       uint32_t limit = limit_type << 24;<br>
+       enum pp_power_sample_window sample_window = to_sensor_dev_attr(attr)->index;<br>
+       uint32_t limit;<br>
         ssize_t size;<br>
         int r;<br>
 <br>
@@ -2774,7 +2774,7 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,<br>
         }<br>
 <br>
         if (is_support_sw_smu(adev)) {<br>
-               smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_CURRENT);<br>
+               smu_get_power_limit(&adev->smu, &limit, PP_PWR_LIMIT_CURRENT, <br>
+sample_window);<br>
                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);<br>
         } else if (pp_funcs && pp_funcs->get_power_limit) {<br>
                 pp_funcs->get_power_limit(adev->powerplay.pp_handle,<br>
@@ -2796,8 +2796,8 @@ static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev,  {<br>
         struct amdgpu_device *adev = dev_get_drvdata(dev);<br>
         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;<br>
-       int limit_type = to_sensor_dev_attr(attr)->index;<br>
-       uint32_t limit = limit_type << 24;<br>
+       enum pp_power_sample_window sample_window = to_sensor_dev_attr(attr)->index;<br>
+       uint32_t limit;<br>
         ssize_t size;<br>
         int r;<br>
 <br>
@@ -2813,7 +2813,7 @@ static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev,<br>
         }<br>
 <br>
         if (is_support_sw_smu(adev)) {<br>
-               smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_DEFAULT);<br>
+               smu_get_power_limit(&adev->smu, &limit, PP_PWR_LIMIT_DEFAULT, <br>
+sample_window);<br>
                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);<br>
         } else if (pp_funcs && pp_funcs->get_power_limit) {<br>
                 pp_funcs->get_power_limit(adev->powerplay.pp_handle,<br>
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h<br>
index 523f9d2982e9..b97b960c2eac 100644<br>
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h<br>
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h<br>
@@ -1262,7 +1262,8 @@ enum smu_cmn2asic_mapping_type {  #if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4)  int smu_get_power_limit(struct smu_context *smu,<br>
                         uint32_t *limit,<br>
-                       enum smu_ppt_limit_level limit_level);<br>
+                       enum pp_power_limit_level pp_limit_level,<br>
+                       enum pp_power_sample_window sample_window);<br>
 <br>
 bool smu_mode1_reset_is_support(struct smu_context *smu);  bool smu_mode2_reset_is_support(struct smu_context *smu); diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c<br>
index 8aff67a667fa..44c1baa2748d 100644<br>
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c<br>
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c<br>
@@ -2168,14 +2168,44 @@ static int smu_set_fan_speed_rpm(void *handle, uint32_t speed)<br>
 <br>
 int smu_get_power_limit(struct smu_context *smu,<br>
                         uint32_t *limit,<br>
-                       enum smu_ppt_limit_level limit_level)<br>
+                       enum pp_power_limit_level pp_limit_level,<br>
+                       enum pp_power_sample_window sample_window)<br>
 {<br>
-       uint32_t limit_type = *limit >> 24;<br>
+       enum smu_ppt_limit_level limit_level;<br>
+       uint32_t limit_type;<br>
         int ret = 0;<br>
 <br>
         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)<br>
                 return -EOPNOTSUPP;<br>
 <br>
+       switch(sample_window) {<br>
+       case PP_PWR_WINDOW_DEFAULT:<br>
+               limit_type = SMU_DEFAULT_PPT_LIMIT;<br>
+               break;<br>
+       case PP_PWR_WINDOW_FAST:<br>
+               limit_type = SMU_FAST_PPT_LIMIT;<br>
+               break;<br>
+       default:<br>
+               return -EOPNOTSUPP;<br>
+               break;<br>
+       }<br>
+<br>
+       switch(pp_limit_level){<br>
+       case PP_PWR_LIMIT_CURRENT:<br>
+               limit_level = SMU_PPT_LIMIT_CURRENT;<br>
+               break;<br>
+       case PP_PWR_LIMIT_DEFAULT:<br>
+               limit_level = SMU_PPT_LIMIT_DEFAULT;<br>
+               break;<br>
+       case PP_PWR_LIMIT_MAX:<br>
+               limit_level = SMU_PPT_LIMIT_MAX;<br>
+               break;<br>
+       case PP_PWR_LIMIT_MIN:<br>
+       default:<br>
+               return -EOPNOTSUPP;<br>
+               break;<br>
+       }<br>
+<br>
         mutex_lock(&smu->mutex);<br>
 <br>
         if (limit_type != SMU_DEFAULT_PPT_LIMIT) {<br>
--<br>
2.25.1</p>
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