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[AMD Official Use Only]<br>
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checks should be <font size="2"><span style="font-size:11pt">adev->asic_type >= CHIP_SIENNA_CICHLID so we cover other gfx10.3 asics as well. With that fixed:</span></font></div>
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<font size="2"><span style="font-size:11pt">Reviewed-by: Alex Deucher <alexander.deucher@amd.com></span></font><br>
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<div id="divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" face="Calibri, sans-serif" color="#000000"><b>From:</b> Khaire, Rohit <Rohit.Khaire@amd.com><br>
<b>Sent:</b> Friday, June 4, 2021 10:49 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>; Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; Deng, Emily <Emily.Deng@amd.com>; Liu, Monk <Monk.Liu@amd.com>; Zhou, Peng Ju <PengJu.Zhou@amd.com>;
Chen, Horace <Horace.Chen@amd.com><br>
<b>Cc:</b> Ming, Davis <Davis.Ming@amd.com>; Khaire, Rohit <Rohit.Khaire@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; Khaire, Rohit <Rohit.Khaire@amd.com><br>
<b>Subject:</b> [PATCH] drm/amdgpu: Fix incorrect register offsets for Sienna Cichlid</font>
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<div class="PlainText">RLC_CP_SCHEDULERS and RLC_SPARE_INT0 have different<br>
offsets for Sienna Cichlid<br>
<br>
Signed-off-by: Rohit Khaire <rohit.khaire@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 26 +++++++++++++++++++++-----<br>
1 file changed, 21 insertions(+), 5 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c<br>
index 11a64ca8a5ec..1e1ce1e49c70 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c<br>
@@ -177,6 +177,9 @@<br>
#define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030<br>
#define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0<br>
<br>
+#define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5<br>
+#define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1<br>
+<br>
#define GFX_RLCG_GC_WRITE_OLD (0x8 << 28)<br>
#define GFX_RLCG_GC_WRITE (0x0 << 28)<br>
#define GFX_RLCG_GC_READ (0x1 << 28)<br>
@@ -1489,8 +1492,15 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32<br>
(adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG2) * 4;<br>
scratch_reg3 = adev->rmmio +<br>
(adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3) * 4;<br>
- spare_int = adev->rmmio +<br>
- (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT) * 4;<br>
+<br>
+ if (adev->asic_type == CHIP_SIENNA_CICHLID) {<br>
+ spare_int = adev->rmmio +<br>
+ (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX]<br>
+ + mmRLC_SPARE_INT_0_Sienna_Cichlid) * 4;<br>
+ } else {<br>
+ spare_int = adev->rmmio +<br>
+ (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT) * 4;<br>
+ }<br>
<br>
grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;<br>
grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;<br>
@@ -7410,9 +7420,15 @@ static int gfx_v10_0_hw_fini(void *handle)<br>
if (amdgpu_sriov_vf(adev)) {<br>
gfx_v10_0_cp_gfx_enable(adev, false);<br>
/* Program KIQ position of RLC_CP_SCHEDULERS during destroy */<br>
- tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);<br>
- tmp &= 0xffffff00;<br>
- WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);<br>
+ if (adev->asic_type == CHIP_SIENNA_CICHLID) {<br>
+ tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);<br>
+ tmp &= 0xffffff00;<br>
+ WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);<br>
+ } else {<br>
+ tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);<br>
+ tmp &= 0xffffff00;<br>
+ WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);<br>
+ }<br>
<br>
return 0;<br>
}<br>
-- <br>
2.17.1<br>
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