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[Public]<br>
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Reviewed-by: Alex Deucher <alexander.deucher@amd.com><br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Anson Jacob <Anson.Jacob@amd.com><br>
<b>Sent:</b> Tuesday, June 8, 2021 11:36 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Brol, Eryk <Eryk.Brol@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Wentland, Harry <Harry.Wentland@amd.com>; Zhuo, Qingqing <Qingqing.Zhuo@amd.com>; Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>; Li, Roman <Roman.Li@amd.com>; Jacob, Anson <Anson.Jacob@amd.com>;
Pillai, Aurabindo <Aurabindo.Pillai@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>; R, Bindu <Bindu.R@amd.com><br>
<b>Subject:</b> [PATCH] drm/amd/display: Fix build break</font>
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<div class="PlainText">1. Remove duplicate OTG_PIXEL_RATE_CNTL from dccg_registers<br>
2. Fixes: 18827ee0cc28 ("drm/amd/display: Refactor visual confirm")<br>
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Signed-off-by: Anson Jacob <Anson.Jacob@amd.com><br>
---<br>
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 1 -<br>
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c | 3 +--<br>
2 files changed, 1 insertion(+), 3 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h<br>
index 6bdab06667c9..62904d7ca100 100644<br>
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h<br>
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h<br>
@@ -202,7 +202,6 @@ struct dccg_registers {<br>
#if defined(CONFIG_DRM_AMD_DC_DCN3_1)<br>
uint32_t PHYDSYMCLK_CLOCK_CNTL;<br>
uint32_t PHYESYMCLK_CLOCK_CNTL;<br>
- uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES];<br>
uint32_t DTBCLK_DTO_MODULO[MAX_PIPES];<br>
uint32_t DTBCLK_DTO_PHASE[MAX_PIPES];<br>
uint32_t DCCG_AUDIO_DTBCLK_DTO_MODULO;<br>
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c<br>
index 69da1493b277..e3048f8827d2 100644<br>
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c<br>
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c<br>
@@ -100,6 +100,7 @@ static const struct hw_sequencer_funcs dcn31_funcs = {<br>
.z10_restore = dcn31_z10_restore,<br>
.is_abm_supported = dcn31_is_abm_supported,<br>
.set_disp_pattern_generator = dcn30_set_disp_pattern_generator,<br>
+ .update_visual_confirm_color = dcn20_update_visual_confirm_color,<br>
};<br>
<br>
static const struct hwseq_private_funcs dcn31_private_funcs = {<br>
@@ -129,8 +130,6 @@ static const struct hwseq_private_funcs dcn31_private_funcs = {<br>
.program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,<br>
.update_odm = dcn20_update_odm,<br>
.dsc_pg_control = dcn31_dsc_pg_control,<br>
- .get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,<br>
- .get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color,<br>
.set_hdr_multiplier = dcn10_set_hdr_multiplier,<br>
.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,<br>
.wait_for_blank_complete = dcn20_wait_for_blank_complete,<br>
-- <br>
2.25.1<br>
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