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<div>>From: Liu, Zhan <Zhan.Liu@amd.com></div>
<div>>Sent: Monday, June 21, 2021 9:13 PM</div>
<div>>To: amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>; Cornij, Nikola <Nikola.Cornij@amd.com></div>
<div>>Cc: Liu, Charlene <Charlene.Liu@amd.com></div>
<div>>Subject: [PATCH] drm/amd/display: Enabling eDP no power sequencing with DAL feature mask</div>
<div>> </div>
<div>>[Public]</div>
<div>></div>
<div>>[Why]</div>
<div>>Sometimes, DP receiver chip power-controlled externally by an</div>
<div>>Embedded Controller could be treated and used as eDP,</div>
<div>>if it drives mobile display. In this case,</div>
<div>>we shouldn't be doing power-sequencing, hence we can skip</div>
<div>>waiting for T7-ready and T9-ready."</div>
<div>></div>
<div>>[How]</div>
<div>>Added a feature mask to enable eDP no power sequencing feature.</div>
<div>></div>
<div>>To enable this, set 0x10 flag in amdgpu.dcfeaturemask on</div>
<div>>Linux command line.</div>
<div>></div>
<div>>Signed-off-by: Zhan Liu <zhan.liu@amd.com></div>
<div>Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com></div>
<div>>Change-Id: I15e8fb2979fe3ff5491ccf1ee384693d4dce787c</div>
<div>>---</div>
<div>> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 +</div>
<div>> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++</div>
<div>> drivers/gpu/drm/amd/display/dc/dc.h | 1 +</div>
<div>> .../display/dc/dce110/dce110_hw_sequencer.c | 31 ++++++++++++++++---</div>
<div>> drivers/gpu/drm/amd/include/amd_shared.h | 10 +++---</div>
<div>> 5 files changed, 38 insertions(+), 8 deletions(-)</div>
<div>></div>
<div>>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c</div>
<div>>index 3de1accb060e..b588cf4398db 100644</div>
<div>>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c</div>
<div>>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c</div>
<div>>@@ -159,6 +159,7 @@ int amdgpu_smu_pptable_id = -1;</div>
<div>> * highest. That helps saving some idle power.</div>
<div>> * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default</div>
<div>> * PSR (bit 3) disabled by default</div>
<div>>+ * EDP NO POWER SEQUENCING (bit 4) disabled by default</div>
<div>> */</div>
<div>> uint amdgpu_dc_feature_mask = 2;</div>
<div>> uint amdgpu_dc_debug_mask;</div>
<div>>diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c</div>
<div>>index c0a3119982b0..abba26c8f20a 100644</div>
<div>>--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c</div>
<div>>+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c</div>
<div>>@@ -1174,6 +1174,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)</div>
<div>> if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)</div>
<div>> init_data.flags.disable_fractional_pwm = true;</div>
<div>></div>
<div>>+ if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)</div>
<div>>+ init_data.flags.edp_no_power_sequencing = true;</div>
<div>>+</div>
<div>> init_data.flags.power_down_display_on_boot = true;</div>
<div>></div>
<div>> INIT_LIST_HEAD(&adev->dm.da_list);</div>
<div>>diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h</div>
<div>>index a70697898025..7f1d2d6f9de8 100644</div>
<div>>--- a/drivers/gpu/drm/amd/display/dc/dc.h</div>
<div>>+++ b/drivers/gpu/drm/amd/display/dc/dc.h</div>
<div>>@@ -297,6 +297,7 @@ struct dc_config {</div>
<div>> bool allow_seamless_boot_optimization;</div>
<div>> bool power_down_display_on_boot;</div>
<div>> bool edp_not_connected;</div>
<div>>+ bool edp_no_power_sequencing;</div>
<div>> bool force_enum_edp;</div>
<div>> bool forced_clocks;</div>
<div>> bool allow_lttpr_non_transparent_mode;</div>
<div>>diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c</div>
<div>>index 53dd305fa6b0..013d94c9506a 100644</div>
<div>>--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c</div>
<div>>+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c</div>
<div>>@@ -1023,8 +1023,20 @@ void dce110_edp_backlight_control(</div>
<div>> /* dc_service_sleep_in_milliseconds(50); */</div>
<div>> /*edp 1.2*/</div>
<div>> panel_instance = link->panel_cntl->inst;</div>
<div>>- if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)</div>
<div>>- edp_receiver_ready_T7(link);</div>
<div>>+</div>
<div>>+ if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) {</div>
<div>>+ if (!link->dc->config.edp_no_power_sequencing)</div>
<div>>+ /*</div>
<div>>+ * Sometimes, DP receiver chip power-controlled externally by an</div>
<div>>+ * Embedded Controller could be treated and used as eDP,</div>
<div>>+ * if it drives mobile display. In this case,</div>
<div>>+ * we shouldn't be doing power-sequencing, hence we can skip</div>
<div>>+ * waiting for T7-ready.</div>
<div>>+ */</div>
<div>>+ edp_receiver_ready_T7(link);</div>
<div>>+ else</div>
<div>>+ DC_LOG_DC("edp_receiver_ready_T7 skipped\n");</div>
<div>>+ }</div>
<div>></div>
<div>> if (ctx->dc->ctx->dmub_srv &&</div>
<div>> ctx->dc->debug.dmub_command_table) {</div>
<div>>@@ -1049,8 +1061,19 @@ void dce110_edp_backlight_control(</div>
<div>> dc_link_backlight_enable_aux(link, enable);</div>
<div>></div>
<div>> /*edp 1.2*/</div>
<div>>- if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF)</div>
<div>>- edp_add_delay_for_T9(link);</div>
<div>>+ if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF) {</div>
<div>>+ if (!link->dc->config.edp_no_power_sequencing)</div>
<div>>+ /*</div>
<div>>+ * Sometimes, DP receiver chip power-controlled externally by an</div>
<div>>+ * Embedded Controller could be treated and used as eDP,</div>
<div>>+ * if it drives mobile display. In this case,</div>
<div>>+ * we shouldn't be doing power-sequencing, hence we can skip</div>
<div>>+ * waiting for T9-ready.</div>
<div>>+ */</div>
<div>>+ edp_add_delay_for_T9(link);</div>
<div>>+ else</div>
<div>>+ DC_LOG_DC("edp_receiver_ready_T9 skipped\n");</div>
<div>>+ }</div>
<div>></div>
<div>> if (!enable && link->dpcd_sink_ext_caps.bits.oled)</div>
<div>> msleep(OLED_PRE_T11_DELAY);</div>
<div>>diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h</div>
<div>>index 9ab706cd07ff..d326339cb3cd 100644</div>
<div>>--- a/drivers/gpu/drm/amd/include/amd_shared.h</div>
<div>>+++ b/drivers/gpu/drm/amd/include/amd_shared.h</div>
<div>>@@ -223,10 +223,12 @@ enum amd_harvest_ip_mask {</div>
<div>> };</div>
<div>></div>
<div>> enum DC_FEATURE_MASK {</div>
<div>>- DC_FBC_MASK = 0x1,</div>
<div>>- DC_MULTI_MON_PP_MCLK_SWITCH_MASK = 0x2,</div>
<div>>- DC_DISABLE_FRACTIONAL_PWM_MASK = 0x4,</div>
<div>>- DC_PSR_MASK = 0x8,</div>
<div>>+ //Default value can be found at "uint amdgpu_dc_feature_mask"</div>
<div>>+ DC_FBC_MASK = (1 << 0), //0x1, disabled by default</div>
<div>>+ DC_MULTI_MON_PP_MCLK_SWITCH_MASK = (1 << 1), //0x2, enabled by default</div>
<div>>+ DC_DISABLE_FRACTIONAL_PWM_MASK = (1 << 2), //0x4, disabled by default</div>
<div>>+ DC_PSR_MASK = (1 << 3), //0x8, disabled by default</div>
<div>>+ DC_EDP_NO_POWER_SEQUENCING = (1 << 4), //0x10, disabled by default</div>
<div>> };</div>
<div>></div>
<div>> enum DC_DEBUG_MASK {</div>
<div>>--</div>
>2.25.1
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