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<div class="moz-cite-prefix">On 2021-06-25 1:58 a.m., Aaron Liu
wrote:<br>
</div>
<blockquote type="cite" cite="mid:20210625055812.2274077-1-aaron.liu@amd.com">
<pre class="moz-quote-pre" wrap="">Without driver loaded, SDMA0_UTCL1_PAGE.TMZ_ENABLE is set to 1
by default for all asic. On RV/RN, the sdma goldsetting changes</pre>
</blockquote>
<br>
Ah, that's a good fix!<br>
<br>
A note, I'd rather have "Raven/Renoir" so that we don't scratch our
heads wondering<br>
if "RV/RN" means "recreational vehicle/registered nurse" (which is
what those<br>
abbreviations are used for here in North America).<br>
<br>
So, change this to,<br>
<br>
<i>"On Raven/Renoir the SDMA gold-setting sets
SDMA0_UTCL1_PAGE.TMZ_ENABLE to 0."</i><br>
<br>
("changes" is confusing as it may be used as a plural noun or a
verb...)<br>
<br>
With that change, this patch is:<br>
<br>
Acked-by: Luben Tuikov <a class="moz-txt-link-rfc2396E" href="mailto:luben.tuikov@amd.com"><luben.tuikov@amd.com></a><br>
<br>
Repost it with the description change and my A-C tag and please <b>wait</b>
for Alex to R-B it too next week, before pushing it.<br>
<br>
Regards,<br>
Luben<br>
<br>
<blockquote type="cite" cite="mid:20210625055812.2274077-1-aaron.liu@amd.com">
<pre class="moz-quote-pre" wrap="">
SDMA0_UTCL1_PAGE.TMZ_ENABLE to 0.
This patch restores SDMA0_UTCL1_PAGE.TMZ_ENABLE to 1.
Signed-off-by: Aaron Liu <a class="moz-txt-link-rfc2396E" href="mailto:aaron.liu@amd.com"><aaron.liu@amd.com></a>
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index ede82e0bbd76..97d57c52bff0 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -147,7 +147,7 @@ static const struct soc15_reg_golden golden_settings_sdma_4_1[] = {
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
- SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003e0),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000)
};
@@ -291,7 +291,7 @@ static const struct soc15_reg_golden golden_settings_sdma_4_3[] = {
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
- SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
+ SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003e0),
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x03fbe1fe)
};
</pre>
</blockquote>
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