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[AMD Official Use Only]<br>
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Reviewed-by: Kevin Wang <kevin1.wang@amd.com></div>
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Best Regards,</div>
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Kevin</div>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" color="#000000" style="font-size:11pt"><b>From:</b> Hou, Xiaomeng (Matthew) <Xiaomeng.Hou@amd.com><br>
<b>Sent:</b> Thursday, July 1, 2021 4:31 PM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Wang, Kevin(Yang) <Kevin1.Wang@amd.com>; Lazar, Lijo <Lijo.Lazar@amd.com>; Liu, Aaron <Aaron.Liu@amd.com>; Hou, Xiaomeng (Matthew) <Xiaomeng.Hou@amd.com><br>
<b>Subject:</b> [PATCH] drm/amd/pm: drop smu_v13_0_1.c|h files for yellow carp</font>
<div> </div>
</div>
<div class="BodyFragment"><font size="2"><span style="font-size:11pt">
<div class="PlainText">Since there's nothing special in smu implementation for yellow carp,<br>
it's better to reuse the common smu_v13_0 interfaces and drop the<br>
specific smu_v13_0_1.c|h files.<br>
<br>
Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com><br>
---<br>
drivers/gpu/drm/amd/pm/inc/smu_v13_0.h | 1 +<br>
drivers/gpu/drm/amd/pm/inc/smu_v13_0_1.h | 57 ----<br>
drivers/gpu/drm/amd/pm/swsmu/smu13/Makefile | 2 +-<br>
.../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 26 ++<br>
.../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_1.c | 311 ------------------<br>
.../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 39 ++-<br>
6 files changed, 59 insertions(+), 377 deletions(-)<br>
delete mode 100644 drivers/gpu/drm/amd/pm/inc/smu_v13_0_1.h<br>
delete mode 100644 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_1.c<br>
<br>
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/inc/smu_v13_0.h<br>
index 6119a36b2cba..3fea2430dec0 100644<br>
--- a/drivers/gpu/drm/amd/pm/inc/smu_v13_0.h<br>
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v13_0.h<br>
@@ -26,6 +26,7 @@<br>
#include "amdgpu_smu.h"<br>
<br>
#define SMU13_DRIVER_IF_VERSION_INV 0xFFFFFFFF<br>
+#define SMU13_DRIVER_IF_VERSION_YELLOW_CARP 0x03<br>
#define SMU13_DRIVER_IF_VERSION_ALDE 0x07<br>
<br>
/* MP Apertures */<br>
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1.h b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1.h<br>
deleted file mode 100644<br>
index b6c976a4d578..000000000000<br>
--- a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1.h<br>
+++ /dev/null<br>
@@ -1,57 +0,0 @@<br>
-/*<br>
- * Copyright 2020 Advanced Micro Devices, Inc.<br>
- *<br>
- * Permission is hereby granted, free of charge, to any person obtaining a<br>
- * copy of this software and associated documentation files (the "Software"),<br>
- * to deal in the Software without restriction, including without limitation<br>
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,<br>
- * and/or sell copies of the Software, and to permit persons to whom the<br>
- * Software is furnished to do so, subject to the following conditions:<br>
- *<br>
- * The above copyright notice and this permission notice shall be included in<br>
- * all copies or substantial portions of the Software.<br>
- *<br>
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR<br>
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,<br>
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL<br>
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR<br>
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,<br>
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR<br>
- * OTHER DEALINGS IN THE SOFTWARE.<br>
- *<br>
- */<br>
-#ifndef __SMU_V13_0_1_H__<br>
-#define __SMU_V13_0_1_H__<br>
-<br>
-#include "amdgpu_smu.h"<br>
-<br>
-#define SMU13_0_1_DRIVER_IF_VERSION_INV 0xFFFFFFFF<br>
-#define SMU13_0_1_DRIVER_IF_VERSION_YELLOW_CARP 0x3<br>
-<br>
-/* MP Apertures */<br>
-#define MP0_Public 0x03800000<br>
-#define MP0_SRAM 0x03900000<br>
-#define MP1_Public 0x03b00000<br>
-#define MP1_SRAM 0x03c00004<br>
-<br>
-/* address block */<br>
-#define smnMP1_FIRMWARE_FLAGS 0x3010024<br>
-<br>
-<br>
-#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3)<br>
-<br>
-int smu_v13_0_1_check_fw_status(struct smu_context *smu);<br>
-<br>
-int smu_v13_0_1_check_fw_version(struct smu_context *smu);<br>
-<br>
-int smu_v13_0_1_fini_smc_tables(struct smu_context *smu);<br>
-<br>
-int smu_v13_0_1_get_vbios_bootup_values(struct smu_context *smu);<br>
-<br>
-int smu_v13_0_1_set_default_dpm_tables(struct smu_context *smu);<br>
-<br>
-int smu_v13_0_1_set_driver_table_location(struct smu_context *smu);<br>
-<br>
-int smu_v13_0_1_gfx_off_control(struct smu_context *smu, bool enable);<br>
-#endif<br>
-#endif<br>
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/Makefile b/drivers/gpu/drm/amd/pm/swsmu/smu13/Makefile<br>
index 9b3a8503f5cd..d4c4c495762c 100644<br>
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/Makefile<br>
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/Makefile<br>
@@ -23,7 +23,7 @@<br>
# Makefile for the 'smu manager' sub-component of powerplay.<br>
# It provides the smu management services for the driver.<br>
<br>
-SMU13_MGR = smu_v13_0.o aldebaran_ppt.o smu_v13_0_1.o yellow_carp_ppt.o<br>
+SMU13_MGR = smu_v13_0.o aldebaran_ppt.o yellow_carp_ppt.o<br>
<br>
AMD_SWSMU_SMU13MGR = $(addprefix $(AMD_SWSMU_PATH)/smu13/,$(SMU13_MGR))<br>
<br>
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c<br>
index a3dc7194aaf8..cbce982f2717 100644<br>
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c<br>
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c<br>
@@ -41,6 +41,8 @@<br>
<br>
#include "asic_reg/thm/thm_13_0_2_offset.h"<br>
#include "asic_reg/thm/thm_13_0_2_sh_mask.h"<br>
+#include "asic_reg/mp/mp_13_0_1_offset.h"<br>
+#include "asic_reg/mp/mp_13_0_1_sh_mask.h"<br>
#include "asic_reg/mp/mp_13_0_2_offset.h"<br>
#include "asic_reg/mp/mp_13_0_2_sh_mask.h"<br>
#include "asic_reg/smuio/smuio_13_0_2_offset.h"<br>
@@ -210,6 +212,9 @@ int smu_v13_0_check_fw_version(struct smu_context *smu)<br>
case CHIP_ALDEBARAN:<br>
smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE;<br>
break;<br>
+ case CHIP_YELLOW_CARP:<br>
+ smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_YELLOW_CARP;<br>
+ break;<br>
default:<br>
dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);<br>
smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_INV;<br>
@@ -694,6 +699,27 @@ int smu_v13_0_set_allowed_mask(struct smu_context *smu)<br>
return ret;<br>
}<br>
<br>
+int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)<br>
+{<br>
+ int ret = 0;<br>
+ struct amdgpu_device *adev = smu->adev;<br>
+<br>
+ switch (adev->asic_type) {<br>
+ case CHIP_YELLOW_CARP:<br>
+ if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))<br>
+ return 0;<br>
+ if (enable)<br>
+ ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);<br>
+ else<br>
+ ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);<br>
+ break;<br>
+ default:<br>
+ break;<br>
+ }<br>
+<br>
+ return ret;<br>
+}<br>
+<br>
int smu_v13_0_system_features_control(struct smu_context *smu,<br>
bool en)<br>
{<br>
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_1.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_1.c<br>
deleted file mode 100644<br>
index 61917b49f2bf..000000000000<br>
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_1.c<br>
+++ /dev/null<br>
@@ -1,311 +0,0 @@<br>
-/*<br>
- * Copyright 2020 Advanced Micro Devices, Inc.<br>
- *<br>
- * Permission is hereby granted, free of charge, to any person obtaining a<br>
- * copy of this software and associated documentation files (the "Software"),<br>
- * to deal in the Software without restriction, including without limitation<br>
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,<br>
- * and/or sell copies of the Software, and to permit persons to whom the<br>
- * Software is furnished to do so, subject to the following conditions:<br>
- *<br>
- * The above copyright notice and this permission notice shall be included in<br>
- * all copies or substantial portions of the Software.<br>
- *<br>
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR<br>
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,<br>
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL<br>
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR<br>
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,<br>
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR<br>
- * OTHER DEALINGS IN THE SOFTWARE.<br>
- */<br>
-<br>
-//#include <linux/reboot.h><br>
-<br>
-#define SWSMU_CODE_LAYER_L3<br>
-<br>
-#include "amdgpu.h"<br>
-#include "amdgpu_smu.h"<br>
-#include "smu_v13_0_1.h"<br>
-#include "soc15_common.h"<br>
-#include "smu_cmn.h"<br>
-#include "atomfirmware.h"<br>
-#include "amdgpu_atomfirmware.h"<br>
-#include "amdgpu_atombios.h"<br>
-#include "atom.h"<br>
-<br>
-#include "asic_reg/mp/mp_13_0_1_offset.h"<br>
-#include "asic_reg/mp/mp_13_0_1_sh_mask.h"<br>
-<br>
-/*<br>
- * DO NOT use these for err/warn/info/debug messages.<br>
- * Use dev_err, dev_warn, dev_info and dev_dbg instead.<br>
- * They are more MGPU friendly.<br>
- */<br>
-#undef pr_err<br>
-#undef pr_warn<br>
-#undef pr_info<br>
-#undef pr_debug<br>
-<br>
-int smu_v13_0_1_check_fw_status(struct smu_context *smu)<br>
-{<br>
- struct amdgpu_device *adev = smu->adev;<br>
- uint32_t mp1_fw_flags;<br>
-<br>
- mp1_fw_flags = RREG32_PCIE(MP1_Public |<br>
- (smnMP1_FIRMWARE_FLAGS & 0xffffffff));<br>
-<br>
- if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >><br>
- MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)<br>
- return 0;<br>
-<br>
- return -EIO;<br>
-}<br>
-<br>
-int smu_v13_0_1_check_fw_version(struct smu_context *smu)<br>
-{<br>
- uint32_t if_version = 0xff, smu_version = 0xff;<br>
- uint16_t smu_major;<br>
- uint8_t smu_minor, smu_debug;<br>
- int ret = 0;<br>
-<br>
- ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);<br>
- if (ret)<br>
- return ret;<br>
-<br>
- smu_major = (smu_version >> 16) & 0xffff;<br>
- smu_minor = (smu_version >> 8) & 0xff;<br>
- smu_debug = (smu_version >> 0) & 0xff;<br>
-<br>
- switch (smu->adev->asic_type) {<br>
- case CHIP_YELLOW_CARP:<br>
- smu->smc_driver_if_version = SMU13_0_1_DRIVER_IF_VERSION_YELLOW_CARP;<br>
- break;<br>
-<br>
- default:<br>
- dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);<br>
- smu->smc_driver_if_version = SMU13_0_1_DRIVER_IF_VERSION_INV;<br>
- break;<br>
- }<br>
-<br>
- dev_info(smu->adev->dev, "smu fw reported version = 0x%08x (%d.%d.%d)\n",<br>
- smu_version, smu_major, smu_minor, smu_debug);<br>
-<br>
- /*<br>
- * 1. if_version mismatch is not critical as our fw is designed<br>
- * to be backward compatible.<br>
- * 2. New fw usually brings some optimizations. But that's visible<br>
- * only on the paired driver.<br>
- * Considering above, we just leave user a warning message instead<br>
- * of halt driver loading.<br>
- */<br>
- if (if_version != smu->smc_driver_if_version) {<br>
- dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "<br>
- "smu fw version = 0x%08x (%d.%d.%d)\n",<br>
- smu->smc_driver_if_version, if_version,<br>
- smu_version, smu_major, smu_minor, smu_debug);<br>
- dev_warn(smu->adev->dev, "SMU driver if version not matched\n");<br>
- }<br>
-<br>
- return ret;<br>
-}<br>
-<br>
-int smu_v13_0_1_fini_smc_tables(struct smu_context *smu)<br>
-{<br>
- struct smu_table_context *smu_table = &smu->smu_table;<br>
-<br>
- kfree(smu_table->clocks_table);<br>
- smu_table->clocks_table = NULL;<br>
-<br>
- kfree(smu_table->metrics_table);<br>
- smu_table->metrics_table = NULL;<br>
-<br>
- kfree(smu_table->watermarks_table);<br>
- smu_table->watermarks_table = NULL;<br>
-<br>
- return 0;<br>
-}<br>
-<br>
-static int smu_v13_0_1_atom_get_smu_clockinfo(struct amdgpu_device *adev,<br>
- uint8_t clk_id,<br>
- uint8_t syspll_id,<br>
- uint32_t *clk_freq)<br>
-{<br>
- struct atom_get_smu_clock_info_parameters_v3_1 input = {0};<br>
- struct atom_get_smu_clock_info_output_parameters_v3_1 *output;<br>
- int ret, index;<br>
-<br>
- input.clk_id = clk_id;<br>
- input.syspll_id = syspll_id;<br>
- input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;<br>
- index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,<br>
- getsmuclockinfo);<br>
-<br>
- ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,<br>
- (uint32_t *)&input);<br>
- if (ret)<br>
- return -EINVAL;<br>
-<br>
- output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;<br>
- *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;<br>
-<br>
- return 0;<br>
-}<br>
-<br>
-int smu_v13_0_1_get_vbios_bootup_values(struct smu_context *smu)<br>
-{<br>
- int ret, index;<br>
- uint16_t size;<br>
- uint8_t frev, crev;<br>
- struct atom_common_table_header *header;<br>
- struct atom_firmware_info_v3_4 *v_3_4;<br>
- struct atom_firmware_info_v3_3 *v_3_3;<br>
- struct atom_firmware_info_v3_1 *v_3_1;<br>
-<br>
- index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,<br>
- firmwareinfo);<br>
-<br>
- ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,<br>
- (uint8_t **)&header);<br>
- if (ret)<br>
- return ret;<br>
-<br>
- if (header->format_revision != 3) {<br>
- dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n");<br>
- return -EINVAL;<br>
- }<br>
-<br>
- switch (header->content_revision) {<br>
- case 0:<br>
- case 1:<br>
- case 2:<br>
- v_3_1 = (struct atom_firmware_info_v3_1 *)header;<br>
- smu->smu_table.boot_values.revision = v_3_1->firmware_revision;<br>
- smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;<br>
- smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;<br>
- smu->smu_table.boot_values.socclk = 0;<br>
- smu->smu_table.boot_values.dcefclk = 0;<br>
- smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;<br>
- smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;<br>
- smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;<br>
- smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;<br>
- smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;<br>
- break;<br>
- case 3:<br>
- v_3_3 = (struct atom_firmware_info_v3_3 *)header;<br>
- smu->smu_table.boot_values.revision = v_3_3->firmware_revision;<br>
- smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;<br>
- smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;<br>
- smu->smu_table.boot_values.socclk = 0;<br>
- smu->smu_table.boot_values.dcefclk = 0;<br>
- smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;<br>
- smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;<br>
- smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;<br>
- smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;<br>
- smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;<br>
- break;<br>
- case 4:<br>
- default:<br>
- v_3_4 = (struct atom_firmware_info_v3_4 *)header;<br>
- smu->smu_table.boot_values.revision = v_3_4->firmware_revision;<br>
- smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;<br>
- smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;<br>
- smu->smu_table.boot_values.socclk = 0;<br>
- smu->smu_table.boot_values.dcefclk = 0;<br>
- smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;<br>
- smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;<br>
- smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;<br>
- smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;<br>
- smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;<br>
- break;<br>
- }<br>
-<br>
- smu->smu_table.boot_values.format_revision = header->format_revision;<br>
- smu->smu_table.boot_values.content_revision = header->content_revision;<br>
-<br>
- smu_v13_0_1_atom_get_smu_clockinfo(smu->adev,<br>
- (uint8_t)SMU11_SYSPLL0_SOCCLK_ID,<br>
- (uint8_t)0,<br>
- &smu->smu_table.boot_values.socclk);<br>
-<br>
- smu_v13_0_1_atom_get_smu_clockinfo(smu->adev,<br>
- (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID,<br>
- (uint8_t)0,<br>
- &smu->smu_table.boot_values.dcefclk);<br>
-<br>
- smu_v13_0_1_atom_get_smu_clockinfo(smu->adev,<br>
- (uint8_t)SMU11_SYSPLL0_ECLK_ID,<br>
- (uint8_t)0,<br>
- &smu->smu_table.boot_values.eclk);<br>
-<br>
- smu_v13_0_1_atom_get_smu_clockinfo(smu->adev,<br>
- (uint8_t)SMU11_SYSPLL0_VCLK_ID,<br>
- (uint8_t)0,<br>
- &smu->smu_table.boot_values.vclk);<br>
-<br>
- smu_v13_0_1_atom_get_smu_clockinfo(smu->adev,<br>
- (uint8_t)SMU11_SYSPLL0_DCLK_ID,<br>
- (uint8_t)0,<br>
- &smu->smu_table.boot_values.dclk);<br>
-<br>
- if ((smu->smu_table.boot_values.format_revision == 3) &&<br>
- (smu->smu_table.boot_values.content_revision >= 2))<br>
- smu_v13_0_1_atom_get_smu_clockinfo(smu->adev,<br>
- (uint8_t)SMU11_SYSPLL1_0_FCLK_ID,<br>
- (uint8_t)SMU11_SYSPLL1_2_ID,<br>
- &smu->smu_table.boot_values.fclk);<br>
-<br>
- return 0;<br>
-}<br>
-<br>
-int smu_v13_0_1_set_default_dpm_tables(struct smu_context *smu)<br>
-{<br>
- struct smu_table_context *smu_table = &smu->smu_table;<br>
-<br>
- return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);<br>
-}<br>
-<br>
-int smu_v13_0_1_set_driver_table_location(struct smu_context *smu)<br>
-{<br>
- struct smu_table *driver_table = &smu->smu_table.driver_table;<br>
- int ret = 0;<br>
-<br>
- if (!driver_table->mc_address)<br>
- return 0;<br>
-<br>
- ret = smu_cmn_send_smc_msg_with_param(smu,<br>
- SMU_MSG_SetDriverDramAddrHigh,<br>
- upper_32_bits(driver_table->mc_address),<br>
- NULL);<br>
-<br>
- if (ret)<br>
- return ret;<br>
-<br>
- ret = smu_cmn_send_smc_msg_with_param(smu,<br>
- SMU_MSG_SetDriverDramAddrLow,<br>
- lower_32_bits(driver_table->mc_address),<br>
- NULL);<br>
-<br>
- return ret;<br>
-}<br>
-<br>
-int smu_v13_0_1_gfx_off_control(struct smu_context *smu, bool enable)<br>
-{<br>
- int ret = 0;<br>
- struct amdgpu_device *adev = smu->adev;<br>
-<br>
- switch (adev->asic_type) {<br>
- case CHIP_YELLOW_CARP:<br>
- if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))<br>
- return 0;<br>
- if (enable)<br>
- ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);<br>
- else<br>
- ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);<br>
- break;<br>
- default:<br>
- break;<br>
- }<br>
-<br>
- return ret;<br>
-}<br>
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c<br>
index 7664334d8144..a28352149daa 100644<br>
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c<br>
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c<br>
@@ -25,7 +25,7 @@<br>
<br>
#include "amdgpu.h"<br>
#include "amdgpu_smu.h"<br>
-#include "smu_v13_0_1.h"<br>
+#include "smu_v13_0.h"<br>
#include "smu13_driver_if_yellow_carp.h"<br>
#include "yellow_carp_ppt.h"<br>
#include "smu_v13_0_1_ppsmc.h"<br>
@@ -186,6 +186,22 @@ static int yellow_carp_init_smc_tables(struct smu_context *smu)<br>
return -ENOMEM;<br>
}<br>
<br>
+static int yellow_carp_fini_smc_tables(struct smu_context *smu)<br>
+{<br>
+ struct smu_table_context *smu_table = &smu->smu_table;<br>
+<br>
+ kfree(smu_table->clocks_table);<br>
+ smu_table->clocks_table = NULL;<br>
+<br>
+ kfree(smu_table->metrics_table);<br>
+ smu_table->metrics_table = NULL;<br>
+<br>
+ kfree(smu_table->watermarks_table);<br>
+ smu_table->watermarks_table = NULL;<br>
+<br>
+ return 0;<br>
+}<br>
+<br>
static int yellow_carp_system_features_control(struct smu_context *smu, bool en)<br>
{<br>
struct smu_feature *feature = &smu->smu_feature;<br>
@@ -658,6 +674,13 @@ static ssize_t yellow_carp_get_gpu_metrics(struct smu_context *smu,<br>
return sizeof(struct gpu_metrics_v2_1);<br>
}<br>
<br>
+static int yellow_carp_set_default_dpm_tables(struct smu_context *smu)<br>
+{<br>
+ struct smu_table_context *smu_table = &smu->smu_table;<br>
+<br>
+ return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);<br>
+}<br>
+<br>
static int yellow_carp_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,<br>
long input[], uint32_t size)<br>
{<br>
@@ -1202,17 +1225,17 @@ static int yellow_carp_set_fine_grain_gfx_freq_parameters(struct smu_context *sm<br>
}<br>
<br>
static const struct pptable_funcs yellow_carp_ppt_funcs = {<br>
- .check_fw_status = smu_v13_0_1_check_fw_status,<br>
- .check_fw_version = smu_v13_0_1_check_fw_version,<br>
+ .check_fw_status = smu_v13_0_check_fw_status,<br>
+ .check_fw_version = smu_v13_0_check_fw_version,<br>
.init_smc_tables = yellow_carp_init_smc_tables,<br>
- .fini_smc_tables = smu_v13_0_1_fini_smc_tables,<br>
- .get_vbios_bootup_values = smu_v13_0_1_get_vbios_bootup_values,<br>
+ .fini_smc_tables = yellow_carp_fini_smc_tables,<br>
+ .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,<br>
.system_features_control = yellow_carp_system_features_control,<br>
.send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,<br>
.send_smc_msg = smu_cmn_send_smc_msg,<br>
.dpm_set_vcn_enable = yellow_carp_dpm_set_vcn_enable,<br>
.dpm_set_jpeg_enable = yellow_carp_dpm_set_jpeg_enable,<br>
- .set_default_dpm_table = smu_v13_0_1_set_default_dpm_tables,<br>
+ .set_default_dpm_table = yellow_carp_set_default_dpm_tables,<br>
.read_sensor = yellow_carp_read_sensor,<br>
.is_dpm_running = yellow_carp_is_dpm_running,<br>
.set_watermarks_table = yellow_carp_set_watermarks_table,<br>
@@ -1221,8 +1244,8 @@ static const struct pptable_funcs yellow_carp_ppt_funcs = {<br>
.get_gpu_metrics = yellow_carp_get_gpu_metrics,<br>
.get_enabled_mask = smu_cmn_get_enabled_32_bits_mask,<br>
.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,<br>
- .set_driver_table_location = smu_v13_0_1_set_driver_table_location,<br>
- .gfx_off_control = smu_v13_0_1_gfx_off_control,<br>
+ .set_driver_table_location = smu_v13_0_set_driver_table_location,<br>
+ .gfx_off_control = smu_v13_0_gfx_off_control,<br>
.post_init = yellow_carp_post_smu_init,<br>
.mode2_reset = yellow_carp_mode2_reset,<br>
.get_dpm_ultimate_freq = yellow_carp_get_dpm_ultimate_freq,<br>
-- <br>
2.17.1<br>
<br>
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