<html> <head> <meta http-equiv="Content-Type" content="text/html; charset=us-ascii"> <style type="text/css" style="display:none;"> P {margin-top:0;margin-bottom:0;} </style> </head> <body dir="ltr"> <p style="font-family:Arial;font-size:10pt;color:#008000;margin:15pt;" align="Left"> [Public]<br> </p> <br> <div> <div style="font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);"> As far as I know, umr is the only user of this and it shouldn't cause any problems there.</div> <div style="font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);"> <br> </div> <div style="font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);"> Acked-by: Alex Deucher <alexander.deucher@amd.com></div> <div style="font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);"> <br> </div> <div id="appendonsend"></div> <hr style="display:inline-block;width:98%" tabindex="-1"> <div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Joseph Greathouse <Joseph.Greathouse@amd.com><br> <b>Sent:</b> Tuesday, June 29, 2021 11:47 PM<br> <b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br> <b>Cc:</b> StDenis, Tom <Tom.StDenis@amd.com>; Greathouse, Joseph <Joseph.Greathouse@amd.com><br> <b>Subject:</b> [PATCH] drm/amdgpu: Put MODE register in wave debug info</font> <div> </div> </div> <div class="BodyFragment"><font size="2"><span style="font-size:11pt;"> <div class="PlainText">Add the MODE register into the per-wave debug information.<br> This register holds state such as FP rounding and denorm<br> modes, which exceptions are enabled, and active clamping<br> modes.<br> <br> Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com><br> ---<br> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +<br> drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 1 +<br> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 1 +<br> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 1 +<br> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +<br> 5 files changed, 5 insertions(+)<br> <br> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c<br> index ff7e9f49040e..abcd418e51f1 100644<br> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c<br> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c<br> @@ -4517,6 +4517,7 @@ static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd,<br> dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);<br> dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);<br> dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);<br> + dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);<br> }<br> <br> static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,<br> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c<br> index 3a8d52a54873..6a8dadea40f9 100644<br> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c<br> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c<br> @@ -3027,6 +3027,7 @@ static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, u<br> dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);<br> dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);<br> dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);<br> + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE);<br> }<br> <br> static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,<br> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c<br> index 685212c3ddae..37b4a3db6360 100644<br> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c<br> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c<br> @@ -4198,6 +4198,7 @@ static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, u<br> dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);<br> dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);<br> dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);<br> + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE);<br> }<br> <br> static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,<br> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c<br> index c26e06059466..e0302c23e9a7 100644<br> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c<br> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c<br> @@ -5279,6 +5279,7 @@ static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, u<br> dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);<br> dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);<br> dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);<br> + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE);<br> }<br> <br> static void gfx_v8_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,<br> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c<br> index 044076ec1d03..d42363fcf068 100644<br> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c<br> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c<br> @@ -2080,6 +2080,7 @@ static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, u<br> dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);<br> dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);<br> dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);<br> + dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE);<br> }<br> <br> static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,<br> -- <br> 2.20.1<br> <br> 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